LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 29

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first
passes through an optional delay block. This delay, if selected, ensures no positive input-register hold-time require-
ment when using a global clock.
The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Figure 2-21 shows the input register waveforms for DDR operation and Figure 2-22 shows the design tool primi-
tives. The SDR/SYNC registers have reset and clock enable available.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to the system clock domain. For further discussion of this topic,
see the DDR memory section of this data sheet.
Figure 2-20. Input Register Diagram
(From DDR Polarity
DDRCLKPOL
Control Bus)
DQS Delayed
(From Routing)
(From sysIO
(From DQS
Buffer)
CLK0
Bus)
DI
Delay Block
Fixed Delay
D
D
D-Type
D-Type
DDR Registers
Q
Q
2-17
D1
D
D-Type
Q
D0
D2
LatticeXP Family Data Sheet
SDR & Sync
D
/LATCH
D
/LATCH
D-Type
Registers
D-Type
Q
Q
INCK
INDD
IPOS0
IPOS1
Architecture