LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 257

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
June 2007
Introduction
As clock distribution and clock skew management become critical factors in overall system performance, the Phase
Locked Loop (PLL) is increasing in importance for digital designers. Lattice incorporates its sysCLOCK™ PLL tech-
nology in the LatticeECP™, LatticeEC™ and LatticeXP™ device families to help designers manage clocks within
their designs. The PLL components in the LatticeECP/EC and LatticeXP device families share the same architec-
ture. This technical note describes the features and functionalities of the PLLs and their configuration in the isp-
LEVER
Figure 11-1. LatticeECP/EC and LatticeXP sysCLOCK PLL Block Diagram
Features
Functional Description
PLL Divider and Delay Blocks
Input Clock (CLKI) Divider
The CLKI divider is used to control the input clock frequency into the PLL block. It can be set to an integer value of
1 to 16. The divider setting directly corresponds to the divisor of the output clock. The input and output of the input
divider must be within the input and output frequency ranges specified in the device data sheet.
Feedback Loop (CLKFB) Divider
The CLKFB divider is used to divide the feedback signal. Effectively, this multiplies the output clock, because the
divided feedback must speed up to match the input frequency into the PLL block. The PLL block increases the out-
put frequency until the divided feedback frequency equals the input frequency. Like the input divider, the feedback
www.latticesemi.com
DDAIDEL[2:0]
DDAMODE
CLKFB
DDAILAG
CLKI
RST
• Clock synthesis
• Phase shift/duty cycle selection
• Internal and external feedback
• Dynamic delay adjustment
• No external components required
• Lock detect output
DDAIZR
®
design tool. Figure 11-1 shows the block diagram of the PLL.
Divider
CLKFB
Divider
CLKI
LatticeECP/EC and LatticeXP sysCLOCK
Adjust
Delay
Frequency
Phase &
Detector
Internal feedback from CLKOP Divider output
11-1
PLL Design and Usage Guide
Loop
Filter
Controlled
Oscillator
Voltage
Detect
Lock
CLKOP
Divider
Technical Note TN1049
DDAOZR
DDAOLAG
DDAODEL[2:0]
Phase/Duty
CLKOK
Divider
Select
tn1049_04.3
CLKOK
CLKOP
CLKOS
LOCK