LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 352

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
As a consequence, we know that, ignoring everything else (clock skews, registers library setups, etc.), a single
cycle positive edge to positive edge setup available from CLKA to CLKB is: 15.15ns (refer to waveforms in
Figure 17-4). Hence, with 2X multicycle, the resulting setup would be twice that number, or:
Having computed this, the available setup margin is known to be as follows:
Where:
There is no phase relationship between CLKA and CLKB as indicated by the warnings in Figure 17-5. Hence, the
following skews were correctly ignored:
Hence:
Example 2. CLOCK_TO_OUT with PLL Feedback
In this example, ip_macclk_c is assigned to 66 MHZ and the clock to out propagation delays are constrained in the
preference file:
See Figure 17-6 for the block diagram for this example. The resulting Trace report is shown in Figure 17-7.
• No relative phase information exists between both clocks. As a result, Trace does not factor in the skews on
• Td = path delay from clock pin of source register to D pin of destination=2.456 ns. Shown in the Physical
• Ds = destination cell library setup requirement= -0.099 ns. This matches DIN_SET under Constraint Details
• TSB = delay or skew on destination clock CLKB = 7.889 ns. Shown in the Clock Skews detail section of
• TSA = delay or skew on source clock CLKA = 7.699 ns. Shown in the Clock Skews detail section of Trace
• M = (30.3 - 2.46) - (-0.099) = 27.9 ns. This matches the number in the “PASSED” section at the top of the
FREQUENCY NET "ip_macclk_c" 66 MHZ;
CLOCK_TO_OUT ALLPORTS 7.000000 ns CLKPORT "ip_macclk" ;
either clock.
Path Details section of Trace report.
section of the .twr Trace report.
Trace report.
report.
Trace report.
(shows up as delay constraint under Constraint Details section of Trace report)
M = (Ts - Td) - Ds
Ts = 30.3 ns
17-8
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