LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 310

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
the D[0:7], INITN, and BUSY pins, once all of the configuration data has been received, in order to prevent interfer-
ence with other devices in the daisy chain.
Once the Flow-Through option starts, the device will remain in Flow-Through until the wake up sequence com-
pletes.
Master Clock
If the CFG pins indicate that this is a Master device the CCLK pin will become an output with the frequency set by
the user. The default Master Clock Frequency is 2.5 MHz.
The user can determine the Master Clock frequency by setting the MCCLK_FREQ preference in the Lattice isp-
LEVER design software. One of the first things loaded during configuration is the MCCLK_FREQ parameter; once
this parameter is loaded the frequency changes to the selected value using a glitchless switch. Care should be
exercised not to exceed the frequency specification of the slave devices or the signal integrity capabilities of the
PCB layout. See Table 13-3 for available options.
Security Bit
Setting the security bit prevents readback of the SRAM and Flash from JTAG or the sysCONFIG pins. When the
security bit is set the only operations available are erase and write. The security bit is updated as the last operation
of SRAM configuration or Flash programming. By using on-chip Flash, and setting the security bit, the user can
create a very secure device.
The security bit is accessed via the Preference Editor in ispLEVER design software.
More information on device security can be found in the document FPGA Design Security Issues: Using the
ispXPGA Family of FPGAs to Achieve High Design Security, available on the Lattice Semiconductor web site at
www.latticesemi.com.
Slave Serial Mode
The CCLK pin becomes an input and data at DI is clocked on the rising edge of CCLK. After the device is fully con-
figured, if the Bypass option has been set, data sent to DI will be presented to the next device via the DOUT pin as
shown in Figure 13-4.
Master Serial Mode
In Master Serial mode the device will drive CCLK out to the Slave Serial devices in the chain and the serial PROM
that will provide the bitstream. The Master device accepts the data at DIN on the rising edge of CCLK. The Master
Serial device starts driving CCLK at the beginning of the configuration and continues to drive CCLK until the exter-
nal DONE pin is driven high and an additional 100 to 500 clock cycles have been generated. The CCLK frequency
on power up defaults to 2.5 MHz. The master clock frequency default remains unless a new clock frequency is
loaded from the bitstream.
If a Master Serial device is daisy chained with Slave Serial devices the Bypass option should be used so that over-
flow configuration data is directed to the DOUT pin.
Figure 13-4 shows a serial daisy chain. The daisy chain allows multiple Lattice FPGA devices to be configured
using one configuration storage device. The center device operates in Master Serial with the Bypass option set
Slave Serial (no overload option)
Slave Serial (Bypass ON)
Master Serial (no overload option)
Master Serial (Bypass ON)
Configuration Mode
Configuration Mode
CFG[1]
CFG[1]
0
0
0
0
13-11
CFG[0]
CFG[0]
0
0
1
1
LatticeXP sysCONFIG Usage Guide
CONFIG_MODE
CONFIG_MODE
Master_Serial
Master_Serial
Slave_Serial
Slave_Serial
Chain Mode
Chain Mode
Disable
Bypass
Disable
Bypass