LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 340

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
The following are guidelines for coding the Clock Enable in Lattice Semiconductor FPGAs:
SET / Reset
There are two types of set/reset functions in Lattice Semiconductor FPGAs: Global (GSR) and Local (LSR). The
GSR signal is asynchronous and is used to initialize all registers during configuration. It can be activated either by
an external dedicated pin or from internal logic after configuration. The local SET/Reset signal may be synchro-
nous or asynchronous. GSR is pulsed at power up to either set or reset the registers depending on the configura-
tion of the device. Since the GSR signal has dedicated routing resources that connect to the set and reset pin of
the flip-flops, it saves general-purpose routing and buffering resources and improves overall performance. If asyn-
chronous reset is used in the design, it is recommended to use the GSR for this function, if possible. The reset sig-
nal can be forced to be GSR by the instantiation library element. Synthesis tools will automatically infer GSR if all
• Clock Enable is only supported by FFs, not latches.
• Nibble wide FFs and slices inside a PFU share the same Clock Enable
• All flip-flops in the Lattice Semiconductor FPGA library have a positive clock enable signal
• In the ORCA Series 4 architecture, the Clock Enable signal has the higher priority over synchronous
set/reset by default. However, it can be programmed to have the priority of synchronous LSR over the prior-
ity of Clock Enable. This can be achieved by instantiating the library element in the source code. For exam-
ple, the library element FD1P3IX is a flip-flop that allows synchronous Clear to override Clock Enable.
Users can also specify the priority of generic coding by setting the priority of the control signals differently.
The following examples demonstrate coding methodologies to help the synthesis tools to set the higher pri-
ority of Clock Enable or synchronous LSR.
-- VHDL Example of CE over Sync. LSR
...
COUNT8: process(CLK, GRST)
begin
end process COUNT8;
-- VHDL Example of Sync. LSR Over CE
...
COUNT8: process(CLK, GRST)
begin
if (GRST = '1') then
elsif (CLK'event and CLK='1') then
-- CE Over LSR: Clock Enable has higher priority
end if;
if (GRST = '1') then
elsif (CLK'event and CLK='1') then
-- LSR over CE: Sync. Set/Reset has higher priority
cnt <= (others => '0');
if (CKEN = '1') then
elsif (LRST = '1') then
end if;
cnt <= (others => '0');
if (LRST = '1') then
elsif (CKEN = '1') then
end if;
cnt <= (others => '0');
cnt <= cnt + 1;
cnt <= cnt + 1;
cnt <= (others =>'0');
13-13
// Verilog Example of CE over Sync. LSR
...
always @(posedge CLK or posedge GRST)
begin
end...
// Verilog Example of Sync. LSR Over CE
...
always @(posedge CLK or posedge GRST)
begin
end
...
if (GRST)
else
if (GRST)
else if (LRST)
else if (CKEN)
cnt = 4'b0;
if (CKEN)
else if (LRST)
cnt = 4'b0;
cnt = 4'b0;
cnt = cnt + 1'b1;
HDL Synthesis Coding Guidelines
cnt = cnt + 1'b1;
cnt = 4'b0;
for Lattice Semiconductor FPGAs