LFXP3E-5TN100C Lattice, LFXP3E-5TN100C Datasheet - Page 180

• Manufacturer Part Number: LFXP3E-5TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-5TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 9-6. True Dual Port RAM Attributes for LatticeECP/EC and LatticeXP
The True Dual Port RAM (RAM_DP_TRUE) can be configured as NORMAL, READ BEFORE WRITE or WRITE
THROUGH modes. Each of these modes affects what data comes out of the port Q of the memory during the write
operation followed by the read operation at the same memory location. The READ BEFORE WRITE attribute is
supported for x9 and x18 data widths. Detailed discussions of the WRITE modes and the constraints of the True
Dual Port can be found in Appendix A.
Additionally users can select to enable the output registers for RAM_DP_TRUE. Figures 8-15 through 8-20 show
the internal timing waveforms for the True Dual Port RAM (RAM_DP_TRUE) with these options.
DATA_WIDTH_A
DATA_WIDTH_B
REGMODE_A
REGMODE_B
RESETMODE
CSDECODE_A
CSDECODE_B
WRITEMODE_A
WRITEMODE_B
GSR
Attribute
Data Word Width Port A
Data Word Width Port B
Chip Select Decode for Port A
Chip Select Decode for Port B
Read / Write Mode for Port A
Read / Write Mode for Port B
Register Mode (Pipelining) for Port A
Register Mode (Pipelining) for Port B
Global Set Reset
Selects the Reset type
Description
9-15
1, 2, 4, 9, 18
1, 2, 4, 9, 18
NOREG, OUTREG
NOREG, OUTREG
ASYNC, SYNC
000, 001, 010, 011, 100, 101,
110, 111
000, 001, 010, 011, 100, 101,
110, 111
NORMAL, WRITETHROUGH,
READBEFOREWRITE
NORMAL, WRITETHROUGH,
READBEFOREWRITE
ENABLED, DISABLED
Values
LatticeECP/EC and LatticeXP Devices
ENABLED
NORMAL
NORMAL
Default
NOREG
NOREG
ASYNC
Value
Memory Usage Guide
000
000
1
1
User Selectable
IPexpress
Through
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO