LFXP3E-5TN100C Lattice, LFXP3E-5TN100C Datasheet - Page 350

• Manufacturer Part Number: LFXP3E-5TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-5TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 17-3. Interface Timing Preference File Example
Analyzing Timing Reports
This section describes two examples of actual Trace reports (.twr report file from Trace). The purpose is to analyze
both examples and understand each section of the reports given the design paths constrained.
Example 1. Multicycle Between Two Different Clocks
In this first example, CLKA and CLKB were assigned 104 MHz and 66 MHz frequencies respectively.
In addition, a multicycle constraint was specified as per the preference file:
See Figure 17-4 for the block diagram and waveform for this example. The resulting Trace report is shown in
Figure 17-5.
Figure 17-4. Multicycle Clock Domains Block Diagram and Waveform
FREQUENCY
FREQUENCY NET "CLKB" 66 MHZ ;
MULTICYCLE "M2" START CLKNET "CLKA" END CLKNET "CLKB" 2.000000 X ;
CLKA
CLKB
PERIOD PORT "clk" 30 NS ;
INPUT_SETUP "port_controller*" 9 NS HOLD 3 NS CLKNET "clk";
CLOCK_TO_OUT "port_controller*" 18 NS MIN 3 NS CLKNET "clk";
OUTPUT PORT "port_controller*" LOAD 74 PF ;
TEMPERATURE 96.8 C ;
NET "CLKA" 104 MHZ ;
CLKB
CLKA
7.9 ns
7.7ns
15.15 ns
9.60 ns
7.70 ns
7.90 ns
30.30 ns
17-6
Combinational
Logic
Lattice Semiconductor FPGA
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