LFXP3E-5TN100C Lattice, LFXP3E-5TN100C Datasheet - Page 314

• Manufacturer Part Number: LFXP3E-5TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-5TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Transparent Readback
The ispJTAG Transparent Readback mode allows the user to read the content of the device SRAM or Flash while
the device remains in a functional state. Care must be exercised when reading EBR and distributed RAM, as it is
possible to cause conflicts with accesses from the user design (causing possible data corruption).
The I/O and non-JTAG configuration pins remain active during a Transparent Readback. The device enters the
Transparent Readback mode through a JTAG instruction.
Boundary Scan and BSDL Files
BSDL files for this device can be found on the Lattice web site at www.latticesemi.com. The boundary scan ring
covers all of the I/O pins, as well as the dedicated and dual-purpose sysCONFIG pins.
Power Save Mode
An I/O Power Save mode option is available for the LatticeXP device and will deactivate portions of the I/O cell driv-
ers. This is only valid when using comparator type inputs pins (pins that use VREF), like HSTL, SSTL, etc.
Power Save mode limits some of the functionality of Boundary Scan. For Boundary Scan testing it is recommended
that the I/O Power Save mode be set to OFF so that all of the I/Os will be fully functional.
Wake Up Options
When configuration is complete (the SRAM has been loaded), the device should wake up in a predictable fashion.
The following selections determine how the device will wake up. Two synchronous wake up processes are avail-
able. One automatically wakes the device up when the internal Done bit is set regardless of whether the DONE pin
is held low externally or not, the other waits for the DONE pin to be driven high before starting the wake up process.
The DONE_EX preference determines whether the external DONE pin will control the synchronous wake up.
Wake Up Sequence
Table 13-8 provides a list of the wake up sequences supported by the LatticeXP.
Table 13-8. Wake Up Sequences Supported by LatticeXP
Sequence
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
DONE
DONE
DONE
DONE
DONE
DONE
DONE
Phase T0
GOE, GWDIS, GSR
GOE
GOE
GOE
GOE
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
GOE
GOE, GWDIS
GWDIS
GWDIS, GSR
GOE, GSR
GOE, GWDIS, GSR
Phase T1
13-15
LatticeXP sysCONFIG Usage Guide
GOE, GWDIS, GSR
GWDIS, GSR
GWDIS
GSR
GOE, GWDIS, GSR
GWDIS, GSR
GOE
DONE
DONE
DONE
DONE
DONE
DONE
DONE
GOE, GWDIS, GSR
Phase T2
GOE, GWDIS, GSR
GWDIS, GSR
GSR
GOE, GWDIS, GSR
GOE
GOE, GWDIS, GSR
GSR
GOE
DONE
DONE
GWDIS
GWDIS, GSR
GWDIS, GSR
GOE, GSR
GWDIS
Phase T3