LFXP3E-5TN100C Lattice, LFXP3E-5TN100C Datasheet - Page 358

• Manufacturer Part Number: LFXP3E-5TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-5TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 17-12. Clock Boosting Window
Other important considerations on the practicality of using clock boosting:
Guided Map and PAR
To decrease PAR runtimes after minor changes to a logical design, guided mapping uses a previously generated
.ncd file to “guide” the mapping of the new logical design. Guided mapping can be performed from the Guide File-
name property in the Project Navigator Map Design process, or specified using the command line -g option with
the file name of the guide file. In general, guided MAP should only be used in conjunction with guided PAR.
To Perform Guided Mapping in the Project Navigator
The Map operation will use the guide file to generate the new design file.
To Perform Guided PAR in the Project Navigator
• Some circuits show big improvement, others have no gain. Clock boosting results are very design-depen-
• Clock boosting uses minimum delay values which have not yet been validated at the system level.
• Automatic clock boosting identifies skew and hold time issues. However, after clock boosting is performed,
1. In the Project Navigator Sources window, select the target device.
2. In the Processes window, right-click the Map Design process, and then select Properties to open the
3. Select the Guide Filename property from the property list and type the name of the guide file name in the
4. Click Close to close the dialog box.
1. In the Project Navigator Sources window, select the target device.
2. In the Processes window, right-click the Place & Route Design process and select Properties to open the
3. Under Advanced Options, select the Guide Filename property and type the name of the file in the text
dent.
designers are strongly recommended to run Trace twice, once with regular, maximum delay analysis, and
again with minimum delays. The designer should then read over both resultant .twr timing reports to make
sure there are no timing errors. The minimum delay analysis is done by checking the “Check Hold Times”
checkbox in the Trace Options GUI window.
Properties dialog box.
edit region (<file_name>.ncd).
dialog box.
field.
17-14
Lattice Semiconductor FPGA
Successful Place and Route