LFXP3E-5TN100C Lattice, LFXP3E-5TN100C Datasheet - Page 370

• Manufacturer Part Number: LFXP3E-5TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-5TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
NCLK_DEL
ROUTE
Report:
From the Hold Report below, which was run for MIN conditions:
===============================================================
Preference: INPUT_SETUP PORT “ddr_dq_*” 2.000000 ns CLKNET “pll_nclk” ;
---------------------------------------------------------------------------------------------
---------------
Passed:
(to pll_nclk +)
Logical Details:
Constraint Details:
Physical Path Details:
Name
Source:
Data Path Delay:
Clock Path Delay:
Name
Destination:
•
•
•
-1.609ns INREG_HLD requirement (totaling -0.370ns) by 0.370ns
Feedback path:
t
t
t
0.000ns delay ddr_dq_31 to ddr_dq_31 plus
0.000ns hold offset ddr_dq_31 to clk (totaling 0.000ns) meets
3.144ns delay clk to ddr_dq_31 plus
1.905ns feedback compensation less
Data path ddr_dq_31 to ddr_dq_31:
PD
FDH
FPGA_CLK
= 0.0 ns
The following path meets requirements by 0.370ns
= -1.609 ns
Fanout
0.260ns is the minimum offset for this preference.
Fanout
---
136
32 items scored, 0 timing errors detected.
(min) = 3.144 - 1.905 = 1.239 ns
--------
--------
Cell type
Port
IO-FF In
Delay (ns)
0.385
2.886
3.271
Delay (ns)
0.000
0.000ns
3.144ns
LLHPPLL.CLKIN to
LLHPPLL.NCLK to
(11.8% logic, 88.2% route), 1 logic levels.
(0.0% logic, 0.0% route), 0 logic levels.
Pin type
Pad
Data in
(0.0% logic, 0.0% route), 0 logic levels.
(25.7% logic, 74.3% route), 2 logic levels.
Site
Site
18-10
Cell name
ddr_dq_31
U1_ddrct_np_o4_1_008/U3_databusif/ddr_dqoeZ0Z_31
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
for the DDR SDRAM Controller IP Core
(clock net +/-)
Resource
Resource
Board Timing Guidelines