LFXP3E-5TN100C Lattice, LFXP3E-5TN100C Datasheet - Page 234

• Manufacturer Part Number: LFXP3E-5TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-5TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Internally the DQS and ADDR/CMD signals are clocked using the primary FPGA clock. Therefore, the user will
need to do a 1/4 (one-quarter) clock transfer from the core logic to the DDR registers. Timing can be hard to meet,
so it is recommended that the user first register these signals with the inverted Clock, so that the transfer from the
core logic to I/O registers will only require a 1/2 (half) clock transfer.
The data DQ and DM needs to be delayed by 90° as it leaves the FPGA. This is to center the data and data mask
relative to the DQS when it reaches the DDR memory. This can be accomplished by inverting the CLK to the DQ
and DM data.
The DM signal is generated using the same clock as the DQ data pin. The memory masks the DQ signals if the DM
pins are driven high.
The tristate control for the data output can also be implemented using the ODDRXB primitive.
Figure 10-16 illustrates how to hook up the ODDRXB primitives and the PLL. The DDR Software Primitives section
describes each of the primitives and its instantiation in more detail. Appendix A and Appendix B provide example
code for implementing the complete I/O section of a memory interface for a LatticeECP/EC or LatticeXP device.
Figure 10-16. Software Primitive Implementation for Memory Write
CLK
User logic)
(From
PLL
CLK + 90
CLK
D
D
D
D
D
User logic)
Q
Q
Q
Q
Q
(From
Core Logic
dataout_p
dataout_n
datatri_p
datatri_n
dqstri_p
dqstri_n
“0”
“1”
“0”
“1”
PIO Logic
10-15
CLK
DB
LSR
D
CLK
CLK
CLK
CLK
DA
LSR
LSR
LSR
LSR
CLK
DA
DB
DA
DB
DA
DB
DA
DB
LSR
DA
DB
ODDRXB
ODDRXB
ODDRXB
ODDRXB
ODDRXB
ODDRXB
Q
Q
Q
Q
Q
Q
Q
Q
LatticeECP/EC and LatticeXP
ADDR/
CLKP
CLKN
CMD
DQS
DQ
DM
DDR Usage Guide
DDR Memory
Device