LFXP3E-5TN100C Lattice, LFXP3E-5TN100C Datasheet - Page 351

• Manufacturer Part Number: LFXP3E-5TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-5TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 17-5. Trace Report for Multicycle Clock Domains Example
In Figure 17-5, notice how the path is described in terms of “Logical Details.”
This section shows both the source and destination registers using their unmapped names from the EDIF (Elec-
tronic Data Interchange Format) file. This is a feature that allows the user to recognize the type of logic being ana-
lyzed.
Based on the declared frequencies for both clocks, we already know the following:
================================================================================
Preference: MULTICYCLE "M2" START CLKNET "CLKA"
--------------------------------------------------------------------------------
WARNING - trce: Clock skew between net 'CLKA' and net 'CLKB' not
--------------------------------------------------------------------------------
Passed:
REG_DEL
ROUTE
IN_DEL
ROUTE
MCLK_DEL
ROUTE
IN_DEL
ROUTE
MCLK_DEL
ROUTE
Logical Details:
Constraint Details:
Physical Path Details:
Clock Skew Details:
Source Clock Path:
Destination Clock Path:
• CLKA period = 9.6 ns.
• CLKB period = 15.15 ns.
Source:
Destination:
Delay:
Name
Name
Name
30.302ns delay constraint less
-0.099ns DIN_SET requirement (totaling 30.401ns) by 27.945ns
2.456ns physical path delay PFU_155 to PFU_156 meets
The following path meets requirements by 27.945ns
computed: nets may not be related
Fanout
Fanout
Fanout
40 items scored, 0 timing errors detected.
---
---
---
177
---
---
263
1
1
1
--------
--------
--------
Cell type
FF
FF
Delay (ns)
0.917
1.539
2.456
Delay (ns)
1.192
2.989
0.424
3.094
7.699
Delay (ns)
1.192
3.091
0.424
3.182
7.889
2.456ns
(37.3% logic, 62.7% route), 1 logic levels.
LLPPLL.CLKIN to
(21.0% logic, 79.0% route), 2 logic levels.
ULPPLL.CLKIN to
(20.5% logic, 79.5% route), 2 logic levels.
R22C16.CLK0 to
LLPPLL.MCLK to
ULPPLL.MCLK to
Pin type
Q
Data in
R22C16.Q2 to
AM17.INDD to
AM17.PAD to
C17.INDD to
(37.3% logic, 62.7% route), 1 logic levels.
C17.PAD to
Site
Site
Site
Cell name
v_fifo_bank_1_stfifo0_wr_count_2
v_fifo_bank_1_stfifo0_wr_count_r_2
LLPPLL.CLKIN ip_CLKA_c
ULPPLL.CLKIN ip_CLKB_c
R23C17.DIN2 v_fifo_bank_1_stfifo0_wr_countZ0Z_2 (to CLKB)
LLPPLL.MCLK v_io_ppl3_tx4_1_mtppll_rsp_rsppll_0_0
R22C16.CLK0 CLKA
ULPPLL.MCLK v_io_ppl3_tx4_1_mtppll_mac_macpll_0_0
R23C17.CLK0 CLKB
END CLKNET "CLKB"
R22C16.Q2 PFU_155 (from CLKA)
AM17.INDD ip_CLKA
17-7
C17.INDD ip_CLKB
(clock net +/-)
Resource
Resource
Resource
2.000000 X ;
Lattice Semiconductor FPGA
Successful Place and Route
(from CLKA +)
(to CLKB +)