AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet
AGXD533AAXF0CC
Specifications of AGXD533AAXF0CC
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AGXD533AAXF0CC Summary of contents
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AMD Geode™ GX Processors Data Book August 2005 Publication ID: 31505E AMD Geode™ GX Processors Data Book ...
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Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the ...
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Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1-1. Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 7-5. Typical Video Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 2-1. Graphics Processors Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 6-10. Example of Monochrome Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 6-65. Even Priority Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 9-1. Junction-to-Top Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview 1.1 General Description The AMD Geode™ GX 533@1.1W processor*, Geode GX 500@1.0W processor*, and Geode GX 466@0.9W pro- cessor* are x86 compatible integrated processors specifi- cally designed to power embedded entertainment, education, and business. Serving the needs of consumers ...
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Features General Features Functional blocks include: — CPU Core — GeodeLink™ Control Processor — GeodeLink Interface Units — GeodeLink Memory Controller — Graphics Processor — Display Controller — Video Processor – TFT Controller — GeodeLink PCI Bridge — ...
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Overview Video Processor Hardware video acceleration: — X and Y interpolation using three line buffers — YUV to RGB color space conversion — Horizontal filtering and downscaling Graphics/video overlay and blending: — Overlay of true color video ...
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Overview AMD Geode™ GX Processors Data Book ...
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Architecture Overview The CPU Core provides maximum compatibility with the vast amount of Internet content available while the intelli- gent integration of several other functions, including graph- ics, makes the Geode™ GX processor a true system-level multimedia solution. The Geode ...
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Memory Management Unit The Memory Management Unit (MMU) translates the linear address supplied by the Integer Unit into a physical address to be used by the Cache and TLB Subsystem and the Bus Controller Unit. Memory management procedures ...
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Architecture Overview 2.5 Graphics Processor The Graphics Processor is compatible with the graphics processor used in the GX1 processor with additional func- tions and features to improve performance and ease of use. Like its predecessor, the Geode GX processor’s Graphics ...
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Display Controller The Display Controller performs the following functions: 1) Retrieves graphics, video, and overlay streams from the frame buffer. 2) Serializes the streams. 3) Performs any necessary color lookups and output for- matting. 4) Interfaces to the ...
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Signal Definitions This chapter defines the signals and describes the external interface of the Geode™ GX processor. Figure 3-1 shows the pins organized by their functional groupings. Note that both the CRT and TFT display interface signals are SYSREF RST# ...
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Ball Assignments The Geode GX processor is available with both the CRT and TFT options in the BGU396 (Ball Grid Array Cavity Up, 396 balls) package. However, with the BGD368 package, the CRT and TFT options are packaged ...
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Signal Definitions 3.1.1 Buffer Types The Ball Assignment tables starting on page 23 includes a column labeled “Buffer Type”. The details of each buffer type listed in this column are given in Table 3-3. The col- umn headings in Table ...
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CRT BGD368 Ball Assignments VREF IOUTR IOUTG IOUTB ...
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Signal Definitions Table 3-4. CRT BGD368 Ball Assignment - Sorted by Ball Number Ball Buffer No. Signal Name Type Type A1 V GND --- PWR --- GND --- PWR --- IO ...
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Table 3-4. CRT BGD368 Ball Assignment - Sorted by Ball Number (Continued) Ball Buffer No. Signal Name Type Type K3 SUSP# I 24/Q7 K4 SUSPA# (Strap) I/O 24/ GND --- SS K22 V GND --- SS K23 ...
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Signal Definitions Table 3-4. CRT BGD368 Ball Assignment - Sorted by Ball Number (Continued) Ball Buffer No. Signal Name Type Type AD11 V GND --- SS AD12 GNT1# (Strap) I/O PCI AD13 MD63 I/O SDRAM AD14 MD57 I/O SDRAM AD15 ...
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Table 3-5. CRT BGD368 Ball Assignment - Sorted Alphabetically by Signal Name Ball Signal Name No. Signal Name AD0 L3 CKE1 AD1 M3 CS0# AD2 M1 CS1# AD3 N4 CS2# AD4 P4 CS3# AD5 P1 DEVSEL# AD6 P3 DOT_AV ...
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Signal Definitions Table 3-5. CRT BGD368 Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Ball Signal Name No. Signal Name CORE IO V R22 V CORE CORE IO V T23 V CORE ...
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TFT BGD368 Ball Assignments DRGB9 DRGB2 DRGB16 FPVDD D_AV DRGB8 DRGB1 DRGB17 RSVD IO SS ...
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Signal Definitions Table 3-6. TFT BGD368 Ball Assignment - Sorted by Ball Number Ball Type Buffer No. Signal Name (PD) Type A1 V GND --- PWR --- GND --- PWR --- ...
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Table 3-6. TFT BGD368 Ball Assignment - Sorted by Ball Number (Continued) Ball Type Buffer No. Signal Name (PD) Type K3 SUSP# I 24/Q7 K4 SUSPA# (Strap) I/O 24/ GND --- SS K22 V GND --- SS ...
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Signal Definitions Table 3-6. TFT BGD368 Ball Assignment - Sorted by Ball Number (Continued) Ball Type Buffer No. Signal Name (PD) Type AD11 V GND --- SS AD12 GNT1# (Strap) I/O PCI AD13 MD63 I/O SDRAM AD14 MD57 I/O SDRAM ...
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Table 3-7. TFT BGD368 Ball Assignment - Sorted Alphabetically by Signal Name Ball Signal Name No. Signal Name AD0 L3 DOT_AV DD AD1 M3 DOT_AV SS AD2 M1 DOT_VDD AD3 N4 DOTCLK AD4 P4 DOTREF AD5 P1 DQM0 AD6 ...
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Signal Definitions Table 3-7. TFT BGD368 Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Ball Signal Name No. Signal Name V M22 V CORE CORE IO V R22 V CORE CORE ...
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CRT/TFT BGU396 Ball Assignments RAS1# MD44 V MD39 MD38 SS MEM B V CS0# WE1# MD40 V MD35 MD34 MEM CS1# V MD41 MD45 V ...
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Signal Definitions Table 3-8. CRT/TFT BGU396 Ball Assignment - Sorted by Ball Number Ball Buffer No. Signal Name Type Type A3 V GND -- SS A4 RAS1# O SDRAM A5 MD44 I/O SDRAM A6 V PWR -- MEM A7 MD39 ...
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Table 3-8. CRT/TFT BGU396 Ball Assignment - Sorted by Ball Number (Continued) Ball Buffer No. Signal Name Type Type L2 MD55 I/O SDRAM L3 MD50 I/O SDRAM L4 V PWR -- MEM L11 V GND -- SS L12 V ...
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Signal Definitions Table 3-8. CRT/TFT BGU396 Ball Assignment - Sorted by Ball Number (Continued) Ball Buffer No. Signal Name Type Type AC4 AD21 I/O PCI AC5 AD17 I/O PCI AC6 V GND -- SS AC7 STOP# GND PCI AC8 SYSREF ...
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Table 3-9. CRT/TFT BGU396 Ball Assignment - Sorted Alphabetically by Signal Name Signal Name Ball No. Signal Name AD0 AD14 DEVSEL# AD1 AF13 DISP_EN AD2 AE14 DOT_AV AD3 AC13 DOT_AV AD4 AD11 DOTCLK AD5 AF11 DOTREF AD6 AE11 DOTV ...
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Signal Definitions Table 3-9. CRT/TFT BGU396 Ball Assignment - Sorted Alphabetically by Signal Name (Continued) Signal Name Ball No. Signal Name SDCLK5# L24 V IO SETRES AB26 V IO SMI# AF14 V IO STOP# AC7 V IO SUSP# AF16 V ...
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Signal Descriptions 3.2.1 System Interface Signals Ball No. Signal Name BGD368 SYSREF Y1 RST# AD9 INTR K1 IRQ13 J3 (Strap) SMI# M2 SUSP BGU396 Type Description AC8 I System Reference. PCI input clock; typically 33 or ...
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Signal Definitions 3.2.1 System Interface Signals (Continued) Ball No. Signal Name BGD368 SUSPA# K4 (Strap) SYS_AV AF10 DD SYS_AV AE10 SS SYS_V AF9 DD SYS_V AE9 SS 3.2.2 PCI Interface Signals Ball No. Signal Name BGD368 FRAME# AB3 IRDY# AA4 ...
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PCI Interface Signals (Continued) Ball No. Signal Name BGD368 TRDY# AA2 STOP# Y4 AD[31:0] CRT: See See Table 3-9 Table 3-5 on page 26. TFT: See Table 3-7 on page 32. C/BE[3:0]# AC5, AB4, Y3 BGU396 ...
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Signal Definitions 3.2.2 PCI Interface Signals (Continued) Ball No. Signal Name BGD368 PAR AA3 DEVSEL# AA1 REQ0#, AC7, REQ1#, AC11, REQ2# AD7 GNT0#, AF7, GNT1#, AD12, GNT2# AE7 (Straps) 3.2.3 Memory Interface (DDR) Signals Ball No. Signal Name BGD368 MD[63:0] ...
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Memory Interface (DDR) Signals (Continued) Ball No. Signal Name BGD368 MA[12:0] CRT: See See Table 3-9 Table 3-5 on page 26. TFT: See Table 3-7 on page 32. BA0, Y23, BA1 P24 CS0#, AD26, CS1#, AD25, CS2#, AF23, ...
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Signal Definitions 3.2.3 Memory Interface (DDR) Signals (Continued) Ball No. Signal Name BGD368 SDCLK0, AF17, SDCLK0# AE17 SDCLK1, AF20, SDCLK1# AE20 SDCLK2, Y26, SDCLK2# Y25 SDCLK3, U25, SDCLK3# U26 SDCLK4, A20, SDCLK4# B20 SDCLK5 B17, SDCLK5# A17 MVREF A14 SD_FB_CLK ...
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CRT Interface Signals Ball No. Signal Name BGD368 HSYNC C2 VSYNC C4 DOTCLK G1 DOTREF U1 DOT_AV A9 DD DOT_AV A10 SS DOT_V B11 DD SETRES C6 VREF B5 IOUTR B6 (Video DAC) IOUTG B7 (Video DAC) IOUTB ...
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Signal Definitions 3.2.4.3 TFT Interface Signals Ball No. Signal Name BGD368 DRGB[23:0] See Table 3-7 See Table 3-9 on page 32. HSYNC C2 VSYNC C4 DOTCLK G1 DOTREF U1 DOT_AV A9 DD DOT_AV A10 SS DOT_V B11 DD DISP_EN C9 ...
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Power and Ground Signals Ball No. Signal Name ( ) Note 1 BGD368 V CRT: See See Table 3-9 CORE Table 3-5 on page 26 TFT: See Table 3 page 32. Note 1. ...
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GeodeLink™ Interface Unit Many traditional architectures use buses to connect mod- ules together, which usually requires unique addressing for each register in every module. This requires that some kind of house-keeping be done as new modules are designed and new ...
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GLMC Not Used GLIU0 GLIU0 GLIU1 Not Used GLIU1 6 Not Used 4 GLPCI GLPCI Figure 4-1. GeodeLink™ Architecture 50 4.1.2 Port Addressing Exceptions There are some exceptions to the ...
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GeodeLink™ Interface Unit Table 4-1 shows the MSR port address to access all the modules in a Geode GX processor and Geode companion device system with the CPU Core as the source module. Included in the table is the MSR ...
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Table 4-2. GLIU Memory Descriptor Address Hit and Routing Description Descriptor Function Description P2D_BM, Checks that the physical address supplied by the device’s request on address bits [31:12] with a logical AND with P2D_BMO PMASK bits of the descriptor ...
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GeodeLink™ Interface Unit 4.1.3.2 I/O Routing and Translation I/O addresses are routed and are never translated. I/O request routing is performed with a choice of two descriptor types. Each GLIU may have any number of each descriptor type. The IOD ...
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GeodeLink™ Inteface Unit Register Descriptions All GeodeLink Interface Unit (GLIU) registers are Model Specific Registers (MSRs) and are accessed through the RDMSR and WRMSR instructions. The registers associated with the GLIU are the Standard GeodeLink Device (GLD) MSRs, ...
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GeodeLink™ Inteface Unit Register Descriptions Table 4-5. GLIU Specific MSRs Summary (Continued) MSR Address Type Register GLIU0: 1000008Ah RO Reserved GLIU1: 4000008Ah GLIU0: 1000008Bh RO WHO AM I (WHOAMI) GLIU1: 4000008Bh GLIU0: 1000008Ch R/W Slave Disable (SLV_DIS) GLIU1: 4000008Ch GLIU0: ...
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Table 4-5. GLIU Specific MSRs Summary (Continued) MSR Address Type Register GLIU0: 100000C2h R/W Request Compare Value GLIU1: 400000C2h (RQ_COMPARE_VAL[1]) GLIU0: 100000C3h R/W Request Compare Mask GLIU1: 400000C3h (RQ_COMPARE_MASK[1]) GLIU0: 100000C4h R/W Request Compare Value GLIU1: 400000C4h (RQ_COMPARE_VAL[2]) GLIU0: ...
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GeodeLink™ Inteface Unit Register Descriptions Table 4-5. GLIU Specific MSRs Summary (Continued) MSR Address Type Register GLIU0: 100000DFh R/W Data Compare Mask High GLIU1: 400000DFh (DA_COMPARE_MASK_HI[3]) Table 4-6. GLIU P2D Descriptor MSRs Summary MSR Address Type Register GLIU0 10000020h- R/W ...
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Table 4-7. GLIU IOD Descriptor MSRs Summary MSR Address Type Register GLIU0 100000E0h- R/W IOD Base Mask Descriptors (IOD_BM): 100000E2h IOD_BM[0:3] 100000E3h- R/W IOD Swiss Cheese Descriptors 100000E8h (IOD_SC): IOD_SC[0:5] 100000E9h- R/W IOD Reserved Descriptors 100000FFh GLIU1 400000E0h- R/W ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.1 Standard GeodeLink™ Device MSRs 4.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP) MSR Address GLIU0: 10002000h GLIU1: 40002000h Type RO Reset Value 00000000_000010xxh ...
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GLD SMI MSR (GLD_MSR_SMI) MSR Address GLIU0: 10002002h GLIU1: 40002002h Type R/W Reset Value 00000000_00000001h The flags are set with internal conditions. The internal conditions are enabled if the corresponding EN bit ...
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GeodeLink™ Inteface Unit Register Descriptions GLD_MSR_SMI Bit Descriptions (Continued) Bit Name Description 32 SSMI_FLAG SSMI Flag. If high, records that an SSMI was generated due to a received event. Event sources are: • Illegal request type to GLIU (Port 0), ...
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GLD Error MSR (GLD_MSR_ERROR) MSR Address GLIU0: 10002003h GLIU1: 40002003h Type R/W Reset Value 00000000_00000001h The flags are set with internal conditions. The internal conditions are enabled if the corresponding EN bit ...
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GeodeLink™ Inteface Unit Register Descriptions GLD_MSR_ERROR Bit Descriptions (Continued) Bit Name Description 42 RQCOMP3_ Request Comparator 3 Error Flag. If high, records that an ERR was generated due to a ERR_FLAG Request Comparator 3 (RQ_COMPARE_VAL3, GLIU0 MSR 100000C6h, GLIU1 MSR ...
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GLD_MSR_ERROR Bit Descriptions (Continued) Bit Name Description 13 DACOMP2_ Data Comparator 2 Error Enable. Write 0 to enable DACOMP2_ERR_FLAG (bit 45) ERR_EN and to allow a Data Comparator 2 (DA_COMPARE_VAL_LO2/DA_COMPARE_VAL_HI2, GLIU0 MSR 100000D8h/100000D9h, GLIU1 MSR 400000D8h/400000D9h) event to generate ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.1.5 GLD Power Management MSR (GLD_MSR_PM) MSR Address GLIU0: 10002004h GLIU1: 40002004h Type R/W Reset Value 00000000_00000000h ...
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GLIU Specific MSRs 4.2.2.1 Coherency (COH) MSR Address GLIU0: 10000080h GLIU1: 40000080h Type R/W Reset Value 00000000_00000000h ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.2.2 Port Active Enable (PAE) MSR Address GLIU0: 10000081h GLIU1: 40000081h Type R/W Reset Value Boot Strap Dependent Ports that are not implemented return 0 (RSVD). Ports that are slave only return 11. (See Section ...
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Arbitration (ARB) MSR Address GLIU0: 10000082h GLIU1: 40000082h Type R/W Reset Value 00000000_00000000h ...
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GeodeLink™ Inteface Unit Register Descriptions Bit Name Description 63:16 RSVD Reserved. Write as read. 15 P7_ASMI_EN Port 7 (GLIU0: Not Used; GLIU1: Not Used) Asynchronous SMI Enable. Write 0 to allow Port 7 to generate an ASMI. ASMI status is ...
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31505E ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.2.6 Debug (DEBUG) MSR Address GLIU0: 10000085h GLIU1: 40000085h Type R/W Reset Value 00000000_00000000h ...
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Bit Name Description 11:6 NP2D_BMO Number of P2D_BMO Descriptors. 5:0 NP2D_BM Number of P2D_BM Descriptors. 4.2.2.8 Number of Outstanding Responses (NOUT_RESP) MSR Address GLIU0: 10000087h GLIU1: 40000087h Type RO Reset Value 00000000_00000000h ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.2.9 Number of Outstanding Write Data (NOUT_WDATA) MSR Address GLIU0: 10000088h GLIU1: 40000088h Type RO Reset Value 00000000_00000000h ...
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Bit Name Description 63:8 RSVD Reserved. Returns 0. 7 P0_SLAVE_ Port 0 (GLIU0: GLIU; GLIU1: GLIU) Slave Only. If low, indicates that Port slave ONLY port. If high, Port master/slave port. 6 P7_SLAVE_ ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.2.12 Slave Disable (SLV_DIS) MSR Address GLIU0: 1000008Ch GLIU1: 4000008Ch Type R/W Reset Value 00000000_00000000h The slave disable registers are available for the number of ports on the GLIU. Unused ports return ...
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Descriptor Statistic Counter (STATISTIC_CNT[0:3]) Descriptor Statistic Counter (STATISTIC_CNT[0]) MSR Address GLIU0: 100000A0h GLIU1: 400000A0h Type WO Reset Value 00000000_00000000h Descriptor Statistic Counter (STATISTIC_CNT[1]) MSR Address GLIU0: 100000A4h GLIU1: 400000A4h Type WO Reset Value 00000000_00000000h ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.2.14 Descriptor Statistic Mask (STATISTIC_MASK[0:3] Descriptor Statistic Mask (STATISTIC_MASK[0]) MSR Address GLIU0: 100000A1h GLIU1: 400000A1h Type R/W Reset Value 00000000_00000000h Descriptor Statistic Mask (STATISTIC_MASK[1]) MSR Address GLIU0: 100000A5h GLIU1: 400000A5h Type R/W Reset Value 00000000_00000000h ...
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Descriptor Statistic Action (STATISTIC_ACTION[0:3] Descriptor Statistic Action (STATISTIC_ACTION[0]) MSR Address GLIU0: 100000A2h GLIU1: 400000A2h Type R/W Reset Value 00000000_00000000h Descriptor Statistic Action (STATISTIC_ACTION[1]) MSR Address GLIU0: 100000A6h GLIU1: 400000A6h Type R/W Reset Value 00000000_00000000h ...
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GeodeLink™ Inteface Unit Register Descriptions STATISTIC_ACTION[x] Bit Descriptions (Continued) Bit Name Description 2 HIT_ASMI Assert ASMI on Descriptor Hit. The descriptor hits are ANDed with the masks and then all ORed together. 0: Disable. 1: Enable. 1 HIT_DEC Decrement Counter ...
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Request Compare Mask (RQ_COMPARE_MASK[0:3]) The Request Compare Value and the Request Compare Mask enable traps on specific transactions. A hit to the Request Compare is determined by hit = (RQ_IN & RQ_COMPARE_MASK) == RQ_COMPARE_VAL). A hit can trigger ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.2.18 Data Compare Value Low (DA_COMPARE_VAL_LO[0:3]) The Data Compare Value and the Data Compare Mask enable traps on specific transactions. A hit to the Data Compare is determined by hit = (DA_IN & DA_COMPARE_MASK) == ...
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Data Compare Value High (DA_COMPARE_VAL_HI[0:3] The Data Compare Value and the Data Compare Mask enable traps on specific transactions. A hit to the Data Compare is determined by hit = (DA_IN & DA_COMPARE_MASK) == DA_COMPARE_VAL). A hit can ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.2.20 Data Compare Mask Low (DA_COMPARE_MASK_LO[0:3]) The Data Compare Value and the Data Compare Mask enable traps on specific transactions. A hit to the Data Compare is determined by hit = (DA_IN & DA_COMPARE_MASK) == ...
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Data Compare Mask High (DA_COMPARE_MASK_HI[0:3]) Data Compare Mask High (DA_COMPARE_MASK_HI[0]) MSR Address GLIU0: 100000D3h GLIU1: 400000D3h Type R/W Reset Value 00000000_00000000h Data Compare Mask High (DA_COMPARE_MASK_HI[1]) MSR Address GLIU0: 100000D7h GLIU1: 400000D7h Type R/W Reset Value 00000000_00000000h DA_COMPARE_MASK_HI[x] ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.3 P2D Descriptor MSRs See Section 4.1.3.1 "Memory Routing and Translation" on page 51 for further details on the descriptor usage. 4.2.3.1 P2D Base Mask Descriptor (P2D_BM) These registers set up the Physical-to-Device Base Mask ...
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P2D Base Mask Offset Descriptor (P2D_BMO) GLIU0 P2D_BMO[0:1] MSR Address 10000026h-10000027h Type R/W Reset Value 00000FF0_FFF00000h ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.3.3 P2D Range Descriptor (P2D_R) GLIU0 P2D_R[0] MSR Address 10000028h Type R/W Reset Value 00000000_000FFFFFh ...
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P2D Range Offset Descriptor (P2D_RO) GLIU0 P2D_RO[0:2] MSR Address 10000029h-1000002Bh Type R/W Reset Value 00000000_000FFFFFh ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.3.5 P2D Swiss Cheese Descriptor (P2D_SC) GLIU0 P2D_SC[0] MSR Address 1000002Ch Type R/W Reset Value 00000000_00000000h ...
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I/O Descriptor MSRs See Section 4.1.3.2 "I/O Routing and Translation" on page 53 for further details on the descriptor usage. 4.2.4.1 IOD Base Mask Descriptors (IOD_BM) GLIU0 IOD_BM[0:3] MSR Address 100000E0h-100000E2h Type R/W Reset Value 000000FF_FFF00000h 63 62 ...
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GeodeLink™ Inteface Unit Register Descriptions 4.2.4.2 IOD Swiss Cheese Descriptors (IOD_SC) GLIU0 IOD_SC[0:5] MSR Address 100000E3h-100000E8h Type R/W Reset Value 00000000_00000000h ...
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GeodeLink™ Inteface Unit Register Descriptions AMD Geode™ GX Processors Data Book ...
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CPU Core This section describes the internal operations of the Geode™ GX processor’s CPU Core from a programmer’s point of view. It includes a description of the traditional “core” processing and FPU operations. The integrated function registers are described in ...
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Instruction Set Overview The CPU Core instruction set can be divided into nine types of operations: • Arithmetic • Bit Manipulation • Shift/Rotate • String Manipulation • Control Transfer • Data Transfer • Floating Point • High-Level Language ...
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CPU Core 5.3 Application Register Set The Application Register Set consists of the registers most often used by the applications programmer. These regis- ters are generally accessible, although some bits in the EFLAGS registers are protected. The General Purpose register ...
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General Purpose Registers The General Purpose registers are divided into four data registers, two pointer registers, and two index registers as shown in Table 5-2 on page 95. The Data registers are used by the applications program- mer ...
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CPU Core 5.3.4 EFLAGS Register The EFLAGS register contains status information and con- trols certain operations on the Geode GX processor. The Bit Name Flag Type Description 31:22 RSVD -- Reserved. Set System Identification Bit. The ...
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System Register Set The System Register Set, shown in Table 5-5, consists of registers not generally used by application programmers. These registers are either initialized by the system BIOS or employed by system level programmers who generate operating ...
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CPU Core 5.4.1 Control Registers A map of the Control registers (CR0, CR1, CR2, CR3, and CR4) is shown in Table 5-6 and the bit descriptions are in the tables that follow. (These registers should not be con- fused with ...
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Bit Name Description 31:9 RSVD Reserved. Set to 0 (always returns 0 when read). 8 PCE Performance Counter Enable. Set PCE = 1 to make RDPMC available at nonzero priv- ilege levels. 7 PGE Page Global Enable. Set PGE ...
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CPU Core Table 5-10. CR0 Bit Descriptions (Continued) Bit Name Description 30 CD Cache Disable/Not Write-Through (Snoop). Cache behavior is based on the CR0 CD and NW bits 28:19 RSVD Reserved ...
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Table 5-11. Effects of Various Combinations of EM, TS, and MP Bits CR0[3: 102 Instruction Type MP WAIT 0 Execute 1 ...
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CPU Core Register Descriptions 5.5 CPU Core Register Descriptions All CPU Core registers are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instructions. Each module inside the processor is assigned a 256 regis- ter section of ...
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Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Name 00001210h R/W Suspend-On-Halt Register 00001211h RO XC Mode Register 00001212h RO XC History Register 00001250h R/W Pipeline Control Register 00001301h R/W SMI Control Register 00001302h R/W DMI ...
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CPU Core Register Descriptions Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Name 00001350h R/W XDR1 and XDR0 Extended Breakpoints Register 00001351h R/W XDR3 and XDR2 Extended Breakpoints Register 00001352h R/W XDR5 and XDR4 Opcode Mask and ...
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Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Name 00001713h R/W Instruction Cache Read/Write Tag w/INC Register 00001720h R/W Instruction Memory TLB Index Register 00001721h R/W Instruction Memory TLB MRU Register 00001722h R/W Instruction Memory TLB ...
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CPU Core Register Descriptions Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Name 00001815h R/W Region Configuration Range 5 Register 00001816h R/W Region Configuration Range 6 Register 00001817h R/W Region Configuration Range 7 Register 00001881h R/W CR1 ...
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Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Name 00001A14h RO Reserved Register 00001A40h R/W Mantissa of R0 Register 00001A41h R/W Exponent of R0 Register 00001A42h R/W Mantissa of R1 Register 00001A43h R/W Exponent of R1 ...
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CPU Core Register Descriptions Table 5-13. CPU Core Specific MSRs Summary (Continued) MSR Address Type Name 00003003h R/W CPUID3 Register (Feature Flags) 00003004h R/W CPUID4 Register (N/A) 00003005h R/W CPUID5 Register (N/A) 00003006h R/W CPUID6 Register (Max Extended Levels 1) ...
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Standard GeodeLink™ Device MSRs 5.5.1.1 GLD Capabilities MSR (GLD_MSR_CAP) MSR Address 00002000h Type RO Reset Value 00000000_000860xxh ...
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CPU Core Register Descriptions 5.5.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 00002002h Type R/W Reset Value 00000000_00000000h This register is not used in the CPU Core module. 5.5.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 00002003h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Specific MSRs 5.5.2.1 Time Stamp Counter Register MSR Address 00000010h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.3 Performance Event Counter 1 Register MSR Address 000000C2h Type R/W Reset Value 00000000_00000000h Performance Event Counter 1 Register Map ...
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System Stack Pointer Selector Register MSR Address 00000175h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.7 Performance Event Counter 0 Control Register MSR Address 00000186h Type R/W Reset Value 00000000_00000000h Performance Event Counter 0 Control Register Map ...
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BTB Enable Register MSR Address 00001100h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions Bit Name Description 63:17 RSVD Reserved. Write as read. 16 BTB_TST BTB Test Mode Enable. Enables test mode access to the BTB. 0: BTB_TST disable. 1: BTB_TST enable. 15:9 RSVD Reserved. Write as read. 8:0 BTB_INDX ...
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BTB Data Test Bit Descriptions (Continued) Bit Name Description 33:32 BTB_BP BTB_Branch Predictor. The predictor state for the branch. 00: Strongly not taken. 01: Weakly not taken. 10: Weakly taken. 11: Strongly taken. 31:0 BTB_TADD BTB Target Address. The ...
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CPU Core Register Descriptions 5.5.2.13 Return Stack Data Test Register MSR Address 0000110Bh Type R/W Reset Value 0000000x_xxxxxxxxh ...
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Bit Name Description 63:14 RSVD Reserved. Write as read. 13 BTB_TRCS BTB Tag RAM Compare Status (Read Only). The active high compare status value for (RO) the BTB Tag RAMs. 12 BTB_TRGO BTB Tag RAM Go (Read Only). Pass/fail ...
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CPU Core Register Descriptions 5.5.2.15 Suspend-On-Halt Register MSR Address 00001210h Type R/W Reset Value 00000000_00000000h ...
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XC Mode Register MSR Address 00001211h Type RO Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.17 XC History Register MSR Address 00001212h Type RO Reset Value 00000000_00000000h ...
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Pipeline Control Register MSR Address 00001250h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions Bit Name Description 63:6 RSVD (RO) Reserved (Read Only). 5 SMI_EXTL Enable External SMI Pin. Enable SMIs caused by the SMI# pin (BGD368 ball M2; BGU396 ball AF14). 0: Disable. 1: Enable. 4 SMI_IO Enable I/O ...
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Bit Name Description 63:10 RSVD Reserved. Write as read. 9 DMI_TF DMI Trap Flag. 0: Disable DMI single stepping DMI_STALL (bit DMI occurs after the successful execution of each instruc- tion. If DMI_STALL is ...
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CPU Core Register Descriptions 5.5.2.21 Temp[x] Registers Temp0 Register MSR Address 00001310h Type R/W Reset Value 00000000_0000FFF0h Temp1 Register MSR Address 00001311h Type R/W Reset Value 00000000_00000000h ...
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Segment Selector Registers The Segment Selector MSRs provide access to the segment selector and segment flags parts of a segment register. The contents of segment registers should be accessed using MOV or SVDC/RSDC. ES Segment Selector Register MSR ...
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CPU Core Register Descriptions 5.5.2.23 SMM Header Shadow Register MSR Address 0000132Bh Type R/W Reset Value 00000000_00000000h ...
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Base and Limit Registers The segment base/limit MSRs provide access to the segment limit and segment base parts of a segment register. The limit value is the true limit; it does not need to be altered based on ...
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CPU Core Register Descriptions 5.5.2.26 DR1 and DR0 Breakpoints Register MSR Address 00001340h Type R/W Reset Value 00000000_00000000h The DR1/DR0 MSR provides access to Debug Register 1 (DR1) and Debug Register 0 (DR0). DR0 and DR1 each contain either an ...
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DR7 and DR6 Breakpoints Control and Status Register MSR Address 00001343h Type R/W Reset Value 00000400_FFFF0FF0h The DR7/DR6 MSR provides access to Debug Register 7 (DR7) and Debug Register 6 (DR6). DR6 contains status infor- mation about debug ...
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CPU Core Register Descriptions 5.5.2.30 XDR3 and XDR2 Extended Breakpoints Register MSR Address 00001351h Type R/W Reset Value 00000000_00000000h The XDR3/XDR2 MSR provides access to Extended Debug Register 3 (XDR3) and Extended Debug Register 2 (XDR2). XDR2 and XDR3 each ...
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XDR7 and XDR6 Extended Breakpoint Control and Status Register MSR Address 00001353h Type R/W Reset Value 00000000_FFFFAFC0h XDR7 and XDR6 Extended Breakpoint Control and Status Register Map ...
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CPU Core Register Descriptions 5.5.2.34 EX Stage Instruction Pointer Register MSR Address 00001360h Type R/W Reset Value 00000000_00000000h EX Stage Instruction Pointer Register Map ...
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FP Environment Code/Instruction Segment Selector Register MSR Address 00001370h Type R/W Reset Value 00000000_00000000h This MSR provides access to the floating point (FP) environment code segment. The floating point environment data is more easily be accessed using the ...
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CPU Core Register Descriptions 5.5.2.38 FP Environment Operand/Data Segment Selector Register MSR Address 00001372h Type R/W Reset Value 00000000_00000000h This MSR provides access to the floating point (FP) environment data segment. The floating point environment data is more easily be ...
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FP Environment Opcode Register MSR Address 00001374h Type R/W Reset Value 00000000_00000000h This MSR provides access to the floating point (FP) environment opcode. The floating point environment data is more eas- ily be accessed using the FLDENV/FSTENV and ...
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CPU Core Register Descriptions 5.5.2.41 General Registers General Register EAX MSR Address 00001408h Type R/W Reset Value 00000000_00000000h General Register ECX MSR Address 00001409h Type R/W Reset Value 00000000_00000000h General Register EDX MSR Address 0000140Ah Type R/W Reset Value 00000000_00000000h ...
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Extended Flags Register MSR Address 00001418h Type R/W Reset Value 00000000_00000002h ...
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CPU Core Register Descriptions 5.5.2.44 Microcode BIST Register MSR Address 00001428h Type RO Reset Value 00000000_00000000h ...
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Instruction Memory Configuration Bit Descriptions (Continued) Bit Name Description 16 IM_DRT Dynamic Retention Test. Enable dynamic retention test for BIST of tag array. 0: Disable 1: Enable 15:12 IM_LOCK Lock Instruction Memory Cache. Locks Way of the IM cache ...
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CPU Core Register Descriptions 5.5.2.46 Instruction Cache Index Register MSR Address 00001710h Type R/W Reset Value 00000000_00000000h ...
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Instruction Cache Read/Write Tag Register MSR Address 00001712h Type R/W Reset Value 00000000_00000000h Instruction Cache Read/Write Tag Register Map ...
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CPU Core Register Descriptions 5.5.2.49 Instruction Cache Read/Write Tag w/INC Register MSR Address 00001713h Type R/W Reset Value 00000000_00000000h Instruction Cache Read/Write Tag w/INC Register Map ...
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Instruction Memory TLB MRU Register MSR Address 00001721h Type R/W Reset Value 00000000_00000000h Instruction Memory TLB MRU Register Map ...
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CPU Core Register Descriptions Instruction Memory TLB MRU Bit Descriptions Bit Name Description 0 ITLB_MRU0 Most Recent Used 0. 0: Entry index 0 more recent than entry index 1. 1: Entry index 1 more recent than entry index 0. 5.5.2.52 ...
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Instruction Memory TLB Entry w/INC Register MSR Address 00001723h Type R/W Reset Value 00000000_00000000h Instruction Memory TLB Entry w/INC Register Map ...
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CPU Core Register Descriptions 5.5.2.55 Instruction Memory Data BIST Register MSR Address 00001731h Type RO Reset Value 00000000_00000000h Instruction Memory Data BIST Register Map ...
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Data Memory Configuration Bit Descriptions (Continued) Bit Name Description 59:56 PFLOCKT1 Prefetch Lockout of PREFETCHT1. Lock data cache ways (MSB = Way3, LSB = Way0) from allocating or replacing the data on a data prefetch miss from a PREFECTHT1 ...
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CPU Core Register Descriptions Data Memory Configuration Bit Descriptions (Continued) Bit Name Description 11 P4MDIS Disable 4M PTE Cache. 0: Enable 4M PTEs to be cached. Normal operation. 1: Prevent 4M PTEs from being cached and flush any existing entries. ...
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Data Memory Configuration Bit Descriptions (Continued) Bit Name Description 1 MISSER Serialize Load Misses. Stall everything but snoops on a load miss. If any part of the PCI space is marked as cacheable, set this bit. Data accesses are ...
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CPU Core Register Descriptions 5.5.2.58 Region Configuration Bypass Register MSR Address 0000180Ah Type R/W Reset Value 00000000_00000101h Warm Start Value 00000000_00000219h Region Configuration Bypass Register Map ...
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Region Configuration C0000-DFFFF Register MSR Address 0000180Ch Type R/W Reset Value 01010101_01010101h Warm Start Value 19191919_19191919h Region Configuration C0000-DFFFF Register Map ...
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CPU Core Register Descriptions Region Configuration E0000-FFFFF Bit Descriptions Bit Name Description 63:56 RPFC Region Properties for 000FC000-000FFFFF. 55:48 RPF8 Region Properties for 000F8000-000FBFFF. 47:40 RPF4 Region Properties for 000F4000-000FAFFF. 39:32 RPF0 Region Properties for 000F0000-000F3FFF. 31:24 RPEC Region Properties ...
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Region Configuration DMM Register MSR Address 0000180Fh Type R/W Reset Value 00000001_00000001h Warm Start Value xxxxx001_xxxxx005h Region Configuration DMM Register Map ...
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CPU Core Register Descriptions 5.5.2.64 Region Configuration Range Registers Region Configuration Range 0 Register MSR Address 00001810h Type R/W Reset Value 00000000_00000000h Warm Start Value xxxxx000_xxxxx0xxh Region Configuration Range 1 Register MSR Address 00001811h Type R/W Reset Value 00000000_00000000h Warm ...
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Region Properties The region properties consist of a 8-bit field as shown in Table 5-16. Table 5-17 and Table 5-18 describe how the various region properties effect on read and write operations. Note that the cache is always interrogated ...
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CPU Core Register Descriptions Table 5-18. Write Operations vs. Region Properties (Continued Note: “x” indicates setting ...
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CR[x] Copy Registers These are the standard x86 Control Registers CR1, CR2, CR3, and CR4. CR0 is located at MSR 00001420h (see Section 5.5.2.43 on page 140). The contents of CR0-CR4 should only be accessed using the MOV ...
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CPU Core Register Descriptions 5.5.2.66 Data Cache Index Register MSR Address 00001890h Type R/W Reset Value 00000000_00000000h ...
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Bit Name Description 63:0 DC_DATA Data Cache Data. QWORD data to read from or write to the cache line buffer. The buffer is filled from the cache data array on a read to Data Cache Read/Write Tag register (MSR ...
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CPU Core Register Descriptions 5.5.2.69 Data Cache Read/Write Tag w/INC Register MSR Address 00001893h Type R/W Reset Value 00000000_00000000h Data Cache Read/Write Tag w/INC Register Map ...
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L1 Data TLB Index Register MSR Address 00001898h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions L1 Data TLB LRU Bit Descriptions (Continued) Bit Name Description 6 L1DTLB_MRU6 Most Recent Used 6. 0: Entry index 6/7 more recent than entry index 0/1. 1: Entry index 0/1 more recent than entry index 6/7 ...
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Bit Name Description 63:44 L1DTLB_LADD Linear Address. Address [32:12]. 43:35 RSVD (RO) Reserved (Read Only). 34 L1DTLB_WP Write Protect Flag. 0: Page can be written. 1: Page is write protected. 33 L1DTLB_WA_WS Write Allocateblock/Write Serialize Flag. If the page ...
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CPU Core Register Descriptions 5.5.2.74 L1 Data TLB Entry w/INC Register MSR Address 0000189Bh Type R/W Reset Value 00000000_00000000h ...
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Bit Name Description 63:18 RSVD (RO) Reserved (Read Only). 17:16 L2TLB_SEL Cache Array Select. 0x: Select L2 TLB. 10: Select DTE cache. 11: Select 4M PTE cache. 15:6 RSVD (RO) Reserved (Read Only). If L2TLB_SEL (bits [17:16]) = 0x: ...
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CPU Core Register Descriptions L2 TLB/DTE LRU Bit Descriptions (Continued) Bit Name Description 19 L2PTE_MRU2 Most Recent Used 2. 0: Entry 4MPTE index 3 more recent than entry index 0. 1: Entry 4MPTE index 0 more recent than entry index ...
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L2 TLB/DTE Entry Register MSR Address 0000189Eh Type R/W Reset Value 00000000_00000020h ...
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CPU Core Register Descriptions L2 TLB/DTE Entry Bit Descriptions (Continued) Bit Name Description 5 L2TLB_ACC Accessed Flag indicates an entry in the TLB. 4 L2TLB_CD Cache Disable Flag indicates that the page is non-cacheable. 3 L2TLB_WT_BR ...
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Data Memory BIST Register MSR Address 000018C0h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions Data Memory BIST Bit Descriptions (Continued) Bit Name Description 22 DC_TAGCMP2 BIST Results - Data Cache Comparators for Way2 (Read Only). (RO) 0: Fail. 1: Pass. 21 DC_TAGCMP1 BIST Results - Data Cache Comparators for Way1 ...
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Bus Controller Configuration 0 Register MSR Address 00001900h Type R/W Reset Value 00000000_00000111h Bus Controller Configuration 0 Register Map ...
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CPU Core Register Descriptions Bus Controller Configuration 0 Bit Descriptions (Continued) Bit Name Description 6 TSC_DMM Time Stamp Counter Counts during DMM. 0: Disable. 1: Enable. 5 TSC_SUSP Time Stamp Counter Counts during Suspend. 0: Disable. 1: Enable. 4 TSC_SMM ...
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MSR Lock Register MSR Address 00001908h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.84 Real Time Stamp Counter Register MSR Address 00001910h Type R/W Reset Value 00000000_00000000h ...
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Memory Subsystem Array Control Register MSR Address 00001980h Type R/W Reset Value 00000000_00000000h Memory Subsystem Array Control Register Map ...
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CPU Core Register Descriptions FPU Operation Modes Bit Descriptions (Continued) Bit Name Description 1 FPU_SP Limit Results to Single Precision. The FPU datapath is only single-precision width. Operations on single precision numbers can generally be completed in one cycle, but ...
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Bit Name Description 10 SQBIST_PASS Square ROM BIST Pass (Read Only). Indicates pass/fail for the square ROM. (RO) 0: Fail. 1: Pass. 9 SEEDBIST_ Seed ROM BIST Pass (Read Only). Indicates pass/fail for the seed ROM. PASS (RO) 0: ...
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CPU Core Register Descriptions Bit Name Description 63:12 RSVD Reserved. Write as read. 11:0 FPU_CW FPU Control Word. 5.5.2.90 FPU x87 Status Word Register MSR Address 00001A11h Type R/W Reset Value 00000000_00000000h ...
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FPU x87 Tag Word Register MSR Address 00001A12h Type R/W Reset Value 00000000_00000000h ...
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CPU Core Register Descriptions 5.5.2.94 Mantissa of R[x] Registers Mantissa of R0 Register MSR Address 00001A40h Type R/W Reset Value xxxxxxxx_xxxxxxxxh Mantissa of R1 Register MSR Address 00001A42h Type R/W Reset Value xxxxxxxx_xxxxxxxxh Mantissa of R2 Register MSR Address 00001A44h ...
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Exponent of R[x] Registers Exponent of R0 Register MSR Address 00001A41h Type R/W Reset Value 00000000_0000xxxxh Exponent of R1 Register MSR Address 00001A43h Type R/W Reset Value 00000000_0000xxxxh Exponent of R2 Register MSR Address 00001A45h Type R/W Reset ...
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CPU Core Register Descriptions 5.5.2.96 FPU Reserved MSRs MSR addresses 00001A60h through 00001A6F are reserved for internal storage purposes and should not be written to. 5.5.2.97 CPU ID MSRs CPUID0 Register (Standard Levels/Vendor ID String 1) MSR Address 00003000h Type ...
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31505E ...
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Integrated Functions The integrated functions of the Geode™ GX processor are: • GeodeLink™ Memory Controller (GLMC) • Graphics Processor • Display Controller • Video Processor • GeodeLink Control Processor (GLCP) Clock Module SYSREF System PLL DOTCLK PLL DOTREF GeodeLink™ SDCLKs ...
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GeodeLink™ Memory Controller The GeodeLink™ Memory Controller (GLMC) module sup- ports the Unified Memory Architecture (UMA) of the Geode GX processor and controls a 64-bit DDR SDRAM interface without any external buffering. The internal block diagram of the ...
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GeodeLink™ Memory Controller Features • Supports up to 222 MT/S (million transfers per second) DDR SDRAMs • Supports 64-bit data interface • Supports unbuffered DIMMs and SODIMMs • Can maintain open banks at a time • Can ...
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Auto Low Order Interleaving The GLMC requires that module banks [0:1], if both installed, be identical and module banks [2:3], if both installed, be identical. Standard DIMMs and SODIMMs are configured this way. Because of this requirement, when module ...
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GeodeLink™ Memory Controller Table 6-1. LOI - 2 DIMMs, Same Size, 1 DIMM Bank 1 KB Page Size 2 KB Page Size Row Col Row Address 2 Component Banks MA12 A24 -- A25 MA11 A23 -- A24 MA10 A22 -- ...
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Table 6-3. Non-Auto LOI - DIMMs, Different Sizes, 1 DIMM Bank 1 KB Page Size 2 KB Page Size Row Col Row Address 2 Component Banks MA12 A23 -- A24 MA11 A22 -- A23 MA10 A21 ...
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GeodeLink™ Memory Controller 6.1.1.2 Arbitration The pipelining of the GLMC module requests consists of the GLIU0 interface request plus two request buffers: the C (closed) and O (open) slots (see Figure 6-7). A request is accepted at the GLIU0 interface ...
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The first method is the default method. For each read, it looks at the arrival of the earliest byte of data and its data strobe relative to the GLIU0 clock. With the window of arrival unknown, the remaining bytes ...
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GeodeLink™ Memory Controller For the 5-bit delay lines, 10101 is a delay-bypass pattern and provides the smallest delay setting. Then the delays are lengthened with extra bits as shown in Table 6-5. For the 2-bit delays (DQS), the delay line ...
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WRREQX WRREQY rqin dain_ready dain_take wrx0 wrx1 dain drdywx drdyrx w_databuf_out w_dataf m_sd_data m_sd_dqs daout 196 wrx2 wrx3 wry0 wrx0 wrx1 wrx2 wrx3 wry0 wrx0 wrx1 wrx2 wrx3 wrx0 wrx1 wrx2 wrrespx wrrespy Figure 6-10. DDR ...
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GeodeLink™ Memory Controller Register Descriptions 6.2 GeodeLink™ Memory Controller Register Descriptions All GLMC registers are Model Specific Registers (MSRs) and are accessed via the RDMSR and WRMSR instruc- tions. The registers associated with the GLMC are the Standard GeodeLink Device ...
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Table 6-8. GLMC Specific MSRs Summary (Continued) MSR Address Type Register 2000001Ch R/W Performance and Counters 2 (MC_PERF_CNT2) 2000001Dh R/W Clocking and Debug (MC_CFCLK_DBUG) 2000001Eh RO Page Open Status (MC_CF_PG_OPEN) 2000001Fh R/W Read Sync Control (MC_CF_RDSYNC) 20000020h R/W PM ...
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GeodeLink™ Memory Controller Register Descriptions 6.2.1.4 GLD Error MSR (GLD_MSR_ERROR) MSR Address 20002003h Type R/W Reset Value 00000000_00000000h ...
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GLD_MSR_PM Bit Descriptions (Continued) Bit Name Description 31:4 RSVD Reserved. Write as read. 3:2 PMODE1 Power Mode 1 (GLIU and GLMC Clocks). Clock gating for clock domains 0 (GLIU clock) and 1 (GLMC clock). Once the GLMC becomes idle, ...