AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 388

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

MULTISCAN
During manufacturing test, multiple scan chains are avail-
able on the signal pins. Table 6-56 on page 387 identifies
the specific scan behaviors of various pins when in this
mode. The Data register associated with this TAP instruc-
tion is the boundary scan chain and the instruction bits con-
figure the pads such that the boundary scan ring is
providing data into the core and the captured data on the
boundary scan chain is the data coming from the core.
TRI-STATE
This instruction TRI-STATEs all of the signals. The Data
register accessed is the Bypass register.
BYPASS
According IEEE 1149.1, shifting all 1s into the IR must con-
nect the 1-bit Bypass register. The register has no function
except as a storage flip-flop.
6.9.2
One of the major functions of the GLCP is to control the
reset of the Geode GX processor. There are two methods
to reset the Geode GX processor: either by hard reset
using the input signal RST#, or by a soft reset by writing to
an internal MSR in the GLCP.
RST# is used for power-on reset. During power-on reset,
all internal blocks are reset until the release of the RST#
signal.
388
Reset Logic
DOTREF
SYSREF
31505E
SYSPLL
DOTPLL
Figure 6-27. Processor Clock Generation
DOTPLL Clock
SYSPLL Clock
Soft
GLCP_SYSPLL_RST. Soft reset resets all the internal
blocks to their initial status except the TAP controller. TAP
reset is achieved by holding bootstrap[4] low during power-
on reset.
6.9.3
The clock control function controls the generation of the
Geode GX processor internal clocks. For this purpose,
there
GLCP_DOTPLL.
As shown in Figure 6-27, the internal clocks are generated
by SYSPLL and DOTPLL. In normal operation mode
GLCP_SYS_RSTPLL[15] = 0 and GLCP_DOTPLL[15] = 0.
The SYSPLL output clock drives the internal clocks of the
CPU Core, the GeodeLink modules, and SDRAM as
shown in Figure 6-28 on page 389. The output of DOTPLL
drives the DOTCLK, that in turn, drives the Video Proces-
sor and Display Controller modules as shown in Figure 6-
28.
In Bypass mode, when GLCP_SYS_RSTPLL[15] = 1, the
DOTREF input clock drives the clocks of the CPU Core,
GeodeLink
MSR_MCD_DOTPLL[15] = 1, the DOTREF input drives
the DOTCLK.
reset
are
GLCP_SYS_RSTPLL[15]
GLCP_DOTPLL[15]
Clock Control
modules,
two
is
DOTCLK
activated
AMD Geode™ GX Processors Data Book
MSRs:
and
GeodeLink™ Control Processor
GLCP_SYS_RSTPLL
by
SDRAM.
CPU Core Clock
GL Clocks
SDRAM Clocks
writing
Also,
to
register
when
and