AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 382

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.8.4.8
FP Memory Offset 438h
Type
Reset Value
382
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:10
63:32
31:0
Bit
9:8
7:6
5:0
Bit
FRM Memory Data (FMD)
Name
RSVD (RO)
SEL
RSVD (RO)
RIN
Name
RSVD (RO)
RDAT
R/W
00000000_00000000h
31505E
Description
Reserved (Read Only). Reads back as 0.
RGB Memory (FRM RAM) Select. Allows reading or writing to individual R,G, and B
memory FRM RAM locations or writing to all of them at the same time.
00: Read from R FRM RAM but write to RGB FRM RAM.
01: Read or write to R FRM RAM.
10: Read or write to G FRM RAM.
11: Read or write to B FRM RAM.
Reserved (Read Only). Reads back as 0.
FRM Memory Index. This represents the index to the FRM RAM; each RAM is config-
ured as 32x64. It requires two index values to update each row of FRM RAM. For exam-
ple, the 00h index value updates the 32-bit (of 64-bit WORD) LSB of row “0” FRM RAM.
The 01h index value updates the 32-bit (of 64-bit WORD) MSB of row “0” FRM RAM. To
update all the RAM locations the index is programmed only once with starting value, nor-
mally “00”. This is used inside FP to auto increment the FRM RAM locations for every
FRM RAM data access using the FP Memory Offset 438h[31:0].
Description
Reserved (Read Only). Reads back as 0.
RAM Data. This 32-bit data represents FRM RAM data in accordance to the RGB_SEL
(FP Memory Offset 430h[9:8]) and the index value (FP Memory Offset 430h[5:0]).
Note:
When programming the FRM RAM, data writes should always occur in pairs. The
RAM data logic accumulates two 32-bit writes, then commits the full 64 bits.
Undefined results occur if this rule is not followed.
FMD Bit Descriptions
FMI Bit Descriptions
FMD Register Map
RSVD
RDAT
AMD Geode™ GX Processors Data Book
Video Processor Register Descriptions
9
8
7
6
5
4
3
2
1
0