AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 374

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.8.4.2
FP Memory Offset 408h
Type
Reset Value
374
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
Bit
4:0
Bit
31
30
29
28
27
Panel Timing Register 2 (PT2)
Name
HSYNC_PLS_
WIDTH
Name
RSVD (RO)
SP
TFT_PASS_
THRU
LPOL
RSVD
SCRC
R/W
00000000_00000000h
31505E
Description
Horizontal Sync Pulse Width. Stretch the HSYNC pulse width by up to 31 DOTCLKs.
The pulse width is programmable in steps of one DOTCLK. Bits [4:0] are used only for
TFT modes.
00000: Does not generate the HSYNC pulse. The TFT panel uses the default input tim-
ing, which is selected by keeping the HSYNC_SRC bit (bit 27) set to 0. (Default)
00001-11111: The HSYNC pulse width can be varied from one to 31 DOTCLKs.
Description
Reserved (Read Only). Reads back as 0.
Spare. Bit is read/write, but has no function.
TFT Pass Through. Activates the TFT Pass Through mode. In TFT Pass Through
mode, the input timing and the pixel data is passed directly on to the panel interface tim-
ing and the panel data pins to drive the TFT panel. In Pass Through mode the internal FP
TFT logic and timing is not used.
0: Normal mode; uses the TFT logic and timing from the FP.
1: TFT Pass Through mode; FP TFT timing logic functions are not used.
Display Timing Strobe Polarity Select. Selects the polarity of the LDE/MOD pin. This
can be used for panels that require an active low timing LDE interface signal.
0: LDE/MOD signal is active high. (Default)
1: LDE/MOD signal is active low
Reserved. This bit is not defined.
Panel Shift Clock Retrace Activity Control. Programs the shift clock (SHFCLK) to be
either free running, or active only during the display period. Some TFT panels recom-
mend keeping the shift clock running during the retrace time.
0: Shift clock is active only during active display period.
1: Shift clock is free running during the entire frame period.
PSEL
PT1 Bit Descriptions (Continued)
PT2 Bit Descriptions
PT2 Register Map
PIXF
RSVD
RSVD
AMD Geode™ GX Processors Data Book
Video Processor Register Descriptions
9
8
7
RSVD
6
5
4
3
2
1
0