AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 404

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

6.10.2.10 GLCP Clock Active (GLCP_CLKACTIVE)
MSR Address
Type
Reset Value
6.10.2.11 GLCP Clock Mask for Debug Clock Stop Action (GLCP_CLKDISABLE)
MSR Address
Type
Reset Value
This register is reserved for internal testing only. These bits should not be written to
404
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:29
RSVD
Bit
28:0
5
4
3
2
1
0
Bit
Name
GL_BC
CPU_BC
CPU_MSS
CPU_IPIPE
FPUFAST
FPUSLOW
Name
RSVD
CLKACTIVE
4C000011h
RO
Input Determined
4C000012h
R/W
00000000_00000000h
31505E
Description
GeodeLink Clock to Bus Controller Off. When set, disables GL clock to the BC block
in the CPU Core.
CPU Core Clock to Bus Controller Off. When set, disables the CPU Core clock to the
BC block in the CPU Core.
CPU Core Clock to Memory Subsystem Off. When set, disables the CPU Core clock
to MSS block in the CPU Core.
CPU Core Clock to Instruction Pipeline Off. When set, disables the CPU Core clock
to IPIPE block in the CPU Core.
Fast FPU Clock Off. When set, disables the “fast” FPU clock.
Slow FPU Clock Off. When set, disables the “slow” CPU Core clock to FPU.
GLCP_CLKOFF Bit Descriptions (Continued)
Description
Reserved.
Clock Active. This register has bits that, when set, indicate that a block is internally
enabling its own clock. The clock inside a block can still be toggling even though the
GLCP_CLKACTIVE bit is clear if the local clock gating MSR forces the clock to always
be on. Also, the clock can be off even though the GLCP_CLKACTIVE bit is set, if the
GLCP_CLKOFF bit is set in the GLCP_CLKCTL register.
GLCP_CLKACTIVE Bit Descriptions
GLCP_CLKACTIVE Register Map
RSVD
GeodeLink™ Control Processor Register Descriptions
AMD Geode™ GX Processors Data Book
9
8
7
6
5
4
3
2
1
0