AGXD533AAXF0CC AMD (ADVANCED MICRO DEVICES), AGXD533AAXF0CC Datasheet - Page 61

• Manufacturer Part Number: AGXD533AAXF0CC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AGXD533AAXF0CC

• Device Core: X86
• Device Core Size: 64b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.58V
• Operating Supply Voltage (min): 1.42V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 368
• Package Type: BGD
• Lead Free Status / Rohs Status: Not Compliant

GeodeLink™ Inteface Unit Register Descriptions
AMD Geode™ GX Processors Data Book
31:5
Bit
32
4
3
2
1
0
Name
SSMI_FLAG
RSVD
STATCNT3_
ASMI_EN
STATCNT2_
ASMI_EN
STATCNT1_
ASMI_EN
STATCNT0_
ASMI_EN
SSMI_EN
Description
SSMI Flag. If high, records that an SSMI was generated due to a received event. Event
sources are:
• Illegal request type to GLIU (Port 0), meaning anything other than MSR read/write,
• A self-referencing packet (i.e., a packet sent to the GLIU that finds its destination port
• The destination of the packet is to a port where the GLIU slave for that port has been
• Trap on a descriptor with device port set to 0. This is the typical operational use of this
Write 1 to clear; writing 0 has no effect. SSMI_EN (bit 0) must be low to generate SSMI
and set flag.
Reserved. Write as read.
Statistic Counter 3 ASMI Enable. Write 0 to enable STATCNT3_ASMI_FLAG (bit 36)
and to allow a Statistic Counter 3 (GLIU0 MSR 100000ACh, GLIU1 MSR 400000ACh)
event to generate an ASMI.
Statistic Counter 2 ASMI Enable. Write 0 to enable STATCNT2_ASMI_FLAG (bit 35)
and to allow a Statistic Counter 2 (GLIU0 MSR 100000A8h, GLIU1 MSR 400000A8h)
event to generate an ASMI.
Statistic Counter 1 ASMI Enable. Write 0 to enable STATCNT1_ASMI_FLAG (bit 34)
and to allow a Statistic Counter 1 (GLIU0 MSR 100000A4h, GLIU1 MSR 400000A4h)
event to generate an ASMI.
Statistic Counter 0 ASMI Enable. Write 0 to enable STATCNT0_ASMI_FLAG (bit 33)
and to allow a Statistic Counter 0 (GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h)
event to generate an ASMI.
SSMI Enable. Write 0 to enable SSMI_FLAG (bit 32) and to allow a received SSMI event
to generate an SSMI. (See bit 32 description for SSMI event sources.)
GLD_MSR_SMI Bit Descriptions (Continued)
debug request, and null.
is the source port).
disabled.
bit. The data returned with such a trap is the value 0.
31505E
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