MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 204

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

DDC12AB Interface
15.6.5 DDC Status Register (DSR)
Technical Data
204
Address:
RXIF — DDC Receive Interrupt Flag
TXIF — DDC Transmit Interrupt Flag
MATCH — DDC Address Match
Reset:
Read:
Write:
This flag is set after the data receive register (DDRR) is loaded with a
new received data. Once the DDRR is loaded with received data, no
more received data can be loaded to the DDRR register until the CPU
reads the data from the DDRR to clear RXBF flag. RXIF generates an
interrupt request to CPU if the DIEN bit in DCR is also set. This bit is
cleared by writing "0" to it or by reset; or when the DEN = 0.
This flag is set when data in the data transmit register (DDTR) is
downloaded to the output circuit, and that new data can be written to
the DDTR. TXIF generates an interrupt request to CPU if the DIEN bit
in DCR is also set. This bit is cleared by writing "0" to it or when the
DEN = 0.
This flag is set when the received data in the data receive register
(DDRR) is an calling address which matches with the address or its
extended addresses (EXTAD=1) specified in the DADR register.
1 = New data in data receive register (DDRR)
0 = No data received
1 = Data transfer completed
0 = Data transfer in progress
1 = Received address matches DADR
0 = Received address does not match
$0019
RXIF
Bit 7
0
0
Figure 15-6. DDC Status Register (DSR)
= Unimplemented
DDC12AB Interface
TXIF
6
0
0
MATCH
5
0
SRW
4
0
RXAK
3
1
MC68HC908LD60
SCLIF
Freescale Semiconductor
2
0
0
TXBE
1
1
—
Rev. 1.1
RXBF
Bit 0
0