MC68HC908LD60IFU Freescale Semiconductor, MC68HC908LD60IFU Datasheet - Page 208

• Manufacturer Part Number: MC68HC908LD60IFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908LD60IFU

• Cpu Family: HC08
• Device Core Size: 8b
• Frequency (max): 6MHz
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Total Internal Ram Size: 1KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 6-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

DDC12AB Interface
15.7 Programming Considerations
Technical Data
208
When the DDRR is read by the CPU, the receive buffer full flag is cleared
(RXBF = 0), and the next received data is loaded to the DDRR. Each
time when new data is loaded to the DDRR, the RXIF interrupt flag is set,
indicating that new data is available in DDRR.
The sequence of events for slave receive and master receive are
illustrated in
When the DDC module detects an arbitration loss in master mode, it will
release both SDA and SCL lines immediately. But if there are no further
STOP conditions detected, the module will hang up. Therefore, it is
recommended to have time-out software to recover from such ill
condition. The software can start the time-out counter by looking at the
BB (Bus Busy) flag in the DMCR and reset the counter on the completion
of one byte transmission. If a time-out occur, software can clear the DEN
bit (disable DDC module) to release the bus, and hence clearing the BB
flag. This is the only way to clear the BB flag by software if the module
hangs up due to a no STOP condition received. The DDC can resume
operation again by setting the DEN bit.
Figure
DDC12AB Interface
15-9.
MC68HC908LD60
Freescale Semiconductor
—
Rev. 1.1