UPD75P3216GT Renesas Electronics America, UPD75P3216GT Datasheet - Page 22

• Manufacturer Part Number: UPD75P3216GT
• Manufacturer: Renesas Electronics America

Specifications of UPD75P3216GT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

20
Bit transfer
Arithmetic
Accumulator
manipulation
Increment/
decrement
Instruction
Group
MOV1
ADDS
ADDC
SUBS
SUBC
AND
OR
XOR
RORC
NOT
INCS
DECS
Mnemonic
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
fmem.bit, CY
pmem.@L, CY
@H+mem.bit, CY
A, #n4
XA, #n8
A, @HL
XA, rp’
rp’1, XA
A, @HL
XA, rp’
rp’1, XA
A, @HL
XA, rp’
rp’1, XA
A, @HL
XA, rp’
rp’1, XA
A, #n4
A, @HL
XA, rp’
rp’1, XA
A, #n4
A, @HL
XA, rp’
rp’1, XA
A, #n4
A, @HL
XA, rp’
rp’1, XA
A
A
reg
rp1
@HL
mem
reg
rp’
Operand
No. of Machine
Bytes
2
2
2
2
2
2
1
2
1
2
2
1
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
1
1
2
2
1
2
Data Sheet U10241EJ1V1DS
Cycle
1+S
2+S
1+S
2+S
2+S
1+S
2+S
2+S
1+S
1+S
2+S
2+S
1+S
2+S
2
2
2
2
2
2
1
2
2
1
2
2
2
1
2
2
2
1
2
2
2
1
2
2
1
2
CY←(fmem.bit)
CY←(pmem
CY←(H+mem
(fmem.bit)←CY
(pmem
(H+mem
A←A+n4
XA←XA+n8
A←A+(HL)
XA←XA+rp’
rp’1←rp’1+XA
A, CY←A+(HL)+CY
XA, CY←XA+rp’+CY
rp’1, CY←rp’1+XA+CY
A←A–(HL)
XA←XA–rp’
rp’1←rp’1–XA
A, CY←A–(HL)–CY
XA, CY←XA–rp’–CY
rp’1, CY←rp’1–XA–CY
A←A∧n4
A←A∧(HL)
XA←XA∧rp’
rp’1←rp’1∧XA
A←A∨n4
A←A∨(HL)
XA←XA∨rp’
rp’1←rp’1∨XA
A←A∨n4
A←A∨(HL)
XA←XA∨rp’
rp’1←rp’1∨XA
CY←A
A←A
reg←reg+1
rp1←rp1+1
(HL)←(HL)+1
(mem)←(mem)+1
reg←reg–1
rp’←rp’–1
0
7-2
, A
3-0
+L
3
.bit)←CY
←CY, A
3-2
7-2
3-0
.bit(L
+L
Operation
.bit)
3-2
1-0
n-1
.bit(L
))←CY
←A
1-0
n
))
Addressing
Area
*4
*5
*1
*4
*5
*1
*1
*1
*1
*1
*1
*1
*1
*1
*3
carry
carry
carry
carry
carry
borrow
borrow
borrow
reg=0
rp1=00H
(HL)=0
(mem)=0
reg=FH
rp’=FFH
µ PD75P3216
Condition
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