UPD75P3216GT Renesas Electronics America, UPD75P3216GT Datasheet - Page 9

• Manufacturer Part Number: UPD75P3216GT
• Manufacturer: Renesas Electronics America

Specifications of UPD75P3216GT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.2 Non-port Pins
TI0
PTO0
PTO1
PTO2
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
KR0 to KR3
X1
X2
RESET
MD0 to MD3
D0 to D3
D4 to D7
V
V
V
S12 to S15
S16 to S19
S20 to S23
COM0 to COM3 Output
V
BIAS
LCDCL
SYNC
PP
DD
SS
LC0
Pin Name
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits.
to V
Note 4
Note 4
LC2
2. The V
3. When the split resistor is incorporated
4. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
S12 to S15: V
When the split resistor is not incorporated : High impedance
Output P20
Output
Output P93 to P90
Output
Output P30/MD0
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
—
—
—
—
—
LCX
P13
P21
P22/PCL
P22/PTO2
P23
P01
P02
P03
P00
P10
P60/D0-P63/D3
P30 to P33
P60/KR0-P63/KR3
P50 to P53
P83 to P80
P31/MD1
(X = 0, 1, 2) shown below are selected as the input source for the display outputs.
Shared by
LC1
—
—
—
—
—
—
—
—
—
, COM1 to COM2: V
External event pulse input to timer/event counter
Timer/event counter output
Timer counter output
Clock output
Any frequency output (for buzzer or system clock trimming)
Serial clock I/O
Serial data output
Serial data bus I/O
Serial data input
Serial data bus I/O
Edge detection vectored interrupt input
(detecting both rising and falling edges)
Edge detection vectored interrupt input
(detected edge is selectable). INT0/P10
can select noise elimination circuit
Falling edge detection testable input
Ceramic/crystal oscillation circuit connection for system
clock. If using an external clock, input to X1 and input
inverted phase to X2.
System reset input
Mode selection for program memory (PROM) write/verify
Data bus pin for program memory (PROM) write/verify.
Programmable power supply voltage for program memory
(PROM) write/verify.
For normal operation, connect directly to V
Apply +12.5 V for PROM write/verify.
Positive power supply
Ground
Segment signal output
Segment signal output
Common signal output
Power source for LCD drive
Output for external split resistor cut
Clock output for driving external expansion driver
Clock output for synchronization of external expansion driver
Data Sheet U10241EJ1V1DS
LC2
, COM3: V
: Low level
Function
LC0
Noise elimination
circuit/asynch
is selectable
DD
.
µ PD75P3216
Status
After Reset Type
Note 2
Note 2
Note 3
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
—
—
—
—
—
I/O Circuit
<M>-C
<B>-C
<B>-C
<F>-A
<F>-B
<F>-A
<F>-A
<F>-A
<B>
<B>
M-E
G-A
G-B
E-B
E-B
—
—
—
—
—
—
H
Note 1
7