RC28F256P30B85 Micron Technology Inc, RC28F256P30B85 Datasheet - Page 31

• Manufacturer Part Number: RC28F256P30B85
• Manufacturer: Micron Technology Inc

Specifications of RC28F256P30B85

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 85/17ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 16M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

P30
8.4
8.4.1
Table 15: BEFP Requirements
Note:
1.
August 2008
Order Number: 306666-12
Case Temperature
V
VPP
Setup and Confirm
Programming
Buffer Alignment
CC
Parameter/Issue
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] =
0x00.
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and Status Register bits SR[5,4] are set.
If Buffered programming is attempted while V
SR[4,3] are set. If any errors are detected that have set Status Register bits, the
Status Register should be cleared using the Clear Status Register command.
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash
programming. The enhanced programming algorithm used in BEFP eliminates
traditional programming elements that drive up overhead in device programmer
systems.
BEFP consists of three phases: Setup, Program/Verify, and Exit (see
Flowchart” on page
across 32 data words. Verification occurs in the same phase as programming to
accurately program the flash memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This
enhancement eliminates three write cycles per buffer: two commands and the word
count for each set of 32 data words. Host programmer bus cycles fill the device’s write
buffer followed by a status check. SR[0] indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 32-word array
boundary. This aspect of BEFP saves host programming equipment the address-bus
setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
BEFP Requirements and Considerations
T
Within operating range
Driven to V
Target block unlocked before issuing the BEFP Setup and Confirm commands
The first-word address (WA0) of the block to be programmed must be held constant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired
WA0 must align with the start of an array buffer boundary
C
= 25
°
C ± 5 °C
PPH
83). It uses a write buffer to spread MLC program performance
Requirement
PP
is below V
PPLK
, Status Register bits
Figure 37, “BEFP
1
Notes
Datasheet
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