MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 176

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Enhanced Capture Timer (ECT) Module
13.4.11 16-Bit Pulse Accumulator A Control Register
Read: Anytime
Write: Anytime
Sixteen-bit pulse accumulator A (PACA) is formed by cascading the 8-bit pulse accumulators PAC3 and
PAC2. When PAEN is set, the PACA is enabled. The PACA shares the input pin with IC7.
PAEN — Pulse Accumulator A System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
176
PAEN is independent from TEN. With timer disabled, the pulse accumulator can still function unless
the pulse accumulator is disabled.
For PAMOD bit = 0, event counter mode
For PAMOD bit = 1, gated time accumulation mode
0 = 16-bit pulse accumulator A system disabled. Eight-bit PAC3 and PAC2 can be enabled when
1 = Pulse accumulator A system enabled. The two 8-bit pulse accumulators, PAC3 and PAC2, are
0 = Event counter mode
1 = Gated time accumulation mode
0 = Falling edges on PT7 pin cause the count to be incremented.
1 = Rising edges on PT7 pin cause the count to be incremented.
0 = PT7 input pin high enables M divided by 64 clock to pulse accumulator and the trailing falling
1 = PT7 input pin low enables M divided by 64 clock to pulse accumulator and the trailing rising edge
their related enable bits in ICPACR ($A8) are set. Pulse accumulator input edge flag (PAIF)
function is disabled.
cascaded to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and
PACN2 registers’ contents are, respectively, the high and low byte of the PACA. PA3EN and
PA2EN control bits in ICPACR ($A8) have no effect. Pulse accumulator input edge flag (PAIF)
function is enabled.
edge on PT7 sets the PAIF flag.
on PT7 sets the PAIF flag.
Address: $00A0
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 since
the E ÷ 64 clock is generated by the timer prescaler.
Reset:
Figure 13-29. 16-Bit Pulse Accumulator A Control Register (PACTL)
Read:
Write:
PAMOD
0
0
1
1
Bit 7
0
0
PEDGE
= Unimplemented
PAEN
0
1
0
1
6
0
M68HC12B Family Data Sheet, Rev. 9.1
Falling edge
Rising edge
Divide by 64 clock enabled with pin high level
Divide by 64 clock enabled with pin low level
PAMOD
5
0
NOTE
PEDGE
4
0
Pin Action
CLK1
3
0
CLK0
2
0
PAOVI
1
0
Freescale Semiconductor
Bit 0
PAI
0