MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 177

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

CLK1 and CLK0 — Clock Select Bits
PAOVI — Pulse Accumulator A Overflow Interrupt Enable Bit
PAI — Pulse Accumulator Input Interrupt Enable Bit
13.4.12 Pulse Accumulator A Flag Register
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register.
PAOVF — Pulse Accumulator A Overflow Flag
PAIF — Pulse Accumulator Input Edge Flag
Freescale Semiconductor
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as
an input clock to the timer counter. The change from one selected clock to the other happens
immediately after these bits are written.
Set when the 16-bit pulse accumulator A overflows from $FFFF to $0000 or when 8-bit pulse
accumulator 3 (PAC3) overflows from $FF to $00. This bit is cleared automatically by a write to the
PAFLG register with bit 1 set.
Set when the selected edge is detected at the PT7 input pin. In event mode, the event edge triggers
PAIF and, in gated time accumulation mode, the trailing edge of the gate signal at the PT7 input pin
triggers PAIF. This bit is cleared by a write to the PAFLG register with bit 0 set. Any access to the
PACN3 and PACN2 registers will clear all the flags in this register when TFFCA bit in register TSCR
($86) is set.
0 = Interrupt inhibited
1 = Interrupt requested if PAOVF is set
0 = Interrupt inhibited
1 = Interrupt requested if PAIF is set
Address: $00A1
Reset:
Read:
Write:
Figure 13-30. Pulse Accumulator A Flag Register (PAFLG)
CLK1
0
0
1
1
Bit 7
0
0
CLK0
0
1
0
1
6
0
0
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65,536 as timer counter clock frequency
M68HC12B Family Data Sheet, Rev. 9.1
5
0
0
4
0
0
Clock Source
3
0
0
2
0
0
PAOVF
1
0
PAIF
Bit 0
0
Timer Registers
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