CY7C4282V-10ASC Cypress Semiconductor Corp, CY7C4282V-10ASC Datasheet - Page 11

• Manufacturer Part Number: CY7C4282V-10ASC
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 9 64-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282V-10ASC

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 576 Kb
• Organization: 64Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Architecture
The CY7C4282V/92V consists of an array of 64K to 128K
words of 9 bits each (implemented by a dual-port array of
SRAM cells), a read pointer, a write pointer, control signals
(RCLK, WCLK, REN, WEN, RS), and flags (EF , PAE, PAF , FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition sig-
nified by EF being LOW. All data outputs (Q
after the rising edge of RS. In order for the FIFO to reset to its
default state, the user must not read or write while RS is LOW.
All flags are guaranteed to be valid t
During reset of the FIFO, the state of the XI/LD pin determines
if depth expansion operation is used. For depth expansion op-
eration, XI/LD is tied to XO of the next device. See “Depth
Expansion Configuration” and Figure 3. For standalone or
width expansion configuration, the XI/LD pin must be asserted
LOW during reset.
There is a 0-ns hold time requirement for the XI/LD configura-
tion at the RS deassertion edge. This allows the user to tie
XI/LD to RS directly for applications that do not require access
to the flag offset registers.
FIFO Operation
When the WEN is asserted LOW and FF is HIGH, data present
on the D
of the WCLK signal. Similarly, when the REN is asserted LOW
and EF is HIGH, data in the FIFO memory will be presented
on the Q
edge of RCLK while REN is active. REN must set up t
before RCLK for it to be a valid read function. WEN must occur
t
An Output Enable (OE) pin is provided to three-state the Q
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q
after t
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
even after additional reads occur.
Programming
When LD is held LOW during Reset, this pin is the Load En-
able (LD) for flag offset programming. In this configuration, LD
can be used to access the four 9-bit offset registers contained
in the CY7C4282V/92V for writing or reading data to these
registers.
When the device is configured for programmable flags and
both LD and WEN are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset
least significant bit (LSB) register. The second, third, and
fourth LOW-to-HIGH transitions of WCLK store data in the
empty offset most significant bit (MSB) register, full offset LSB
register, and full offset MSB register, respectively, when LD
and WEN are LOW. The fifth LOW-to-HIGH transition of WCLK
while LD and WEN are LOW writes data to the empty LSB
ENS
before WCLK for it to be a valid write function.
OE
0 8
0 8
. If devices are cascaded, the OE function will only
outputs. New data will be presented on each rising
pins is written into the FIFO on each rising edge
RSF
after RS is taken LOW.
0 8
) go LOW t
0 8
0 8
outputs
outputs
RSF
ENS
0 8
11
register again. Figure 1 shows the registers sizes and default
values for the various device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the LD input HIGH, the FIFO is returned to normal read and
write operation. The next time LD is brought LOW, a write op-
eration stores data in the next offset register in sequence.
The contents of the offset registers can be read to the data
outputs when LD is LOW and REN is LOW. LOW-to-HIGH tran-
sitions of RCLK read register contents to the data outputs.
Writes and reads should not be performed simultaneously on
the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as de-
scribed in Table 1 or the default values are used, the program-
mable Almost Empty flag (PAE) and programmable Almost Full
flag (PAF) states are determined by their corresponding offset
registers and the difference between the read and write
pointers.
Table 1. Writing the Offset Registers
Note:
26. The same selection sequence applies to reading from the registers. REN
8
8
8
8
LD
Figure 1. Offset Register Location and Default Values
0
0
1
1
7
7
7
7
is enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
WEN
64k x 9
0
1
0
1
Default Value = 000h
Default Value = 000h
(MSB)
(MSB)
WCLK
[26]
0
0
0
0
No Operation
Write Into FIFO
No Operation
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
8
8
8
8
7
7
Selection
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
CY7C4282V
CY7C4292V
128kx 9
Default Value = 000h
Default Value = 000h
(MSB)
(MSB)
4282V–16
0
0
0
0