CY7C4282V-10ASC Cypress Semiconductor Corp, CY7C4282V-10ASC Datasheet - Page 12

• Manufacturer Part Number: CY7C4282V-10ASC
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 9 64-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282V-10ASC

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 576 Kb
• Organization: 64Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

The number formed by the empty offset least significant bit
register and empty offset most significant bit register is re-
ferred to as n and determines the operation of PAE. PAE is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n+1) or greater unread words.
The number formed by the full offset least significant bit regis-
ter and full offset most significant bit register is referred to as
m and determines the operation of PAF. PAF is synchronized
to the LOW-to-HIGH transition of WCLK by one flip-flop and is
set LOW when the number of unread words in the FIFO is
greater than or equal to CY7C4282V (64K
CY7C4292V (128K
HIGH transition of WCLK when the number of available mem-
ory locations is greater than m.
Flag Operation
The CY7C4282V/92V devices provide four flag pins to indicate
the condition of the FIFO contents. All flags operate synchro-
nously.
Table 2. Status Flags
0
1 to n
(n+1) to (65536
(65536
65536
Notes:
27. n = Empty Offset (n=7 default value).
28. m = Full Offset (m=7 default value).
[27]
m)
[28]
CY7C4282V
to 65535
(m+1))
m). PAF is set HIGH by the LOW-to-
Number of Words in FIFO
0
1 to n
(n+1) to (131072
(131072
131072
[27]
m) and
m)
[28]
CY7C4292V
to 131071
12
(m+1))
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write op-
erations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclusive-
ly updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regard-
less of the state of REN. EF is synchronized to RCLK, i.e., it is
exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4282V/92V features programmable Almost Empty
and Almost Full Flags. Each flag can be programmed (de-
scribed in the Programming section) a specific distance from
the corresponding boundary flags (Empty or Full). When the
FIFO contains the number of words or fewer for which the flags
have been programmed, the PAF or PAE will be asserted, sig-
nifying that the FIFO is either Almost Full or Almost Empty. See
Table 2 for a description of programmable flags.
FF
H
H
H
H
L
PAF
H
H
H
L
L
CY7C4282V
CY7C4292V
PAE
H
H
H
L
L
EF
H
H
H
H
L