CY7C4282V-10ASC Cypress Semiconductor Corp, CY7C4282V-10ASC Datasheet - Page 14

• Manufacturer Part Number: CY7C4282V-10ASC
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 9 64-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282V-10ASC

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 576 Kb
• Organization: 64Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Depth Expansion Configuration
The CY7C4282V/92V can easily be adapted to applications
requiring more than 64K/128K words of buffering. Figure 3
shows Depth Expansion using three CY7C4282V/92Vs. Max-
imum depth is limited only by signal loading. Follow these
steps:
DATA IN (D)
Figure 3. Block Diagram of 64Kx9/128Kx9 Low-Voltage Deep Sync FIFO Memory
FF
WRITECLOCK (WCLK)
WRITEENABLE (WEN)
RESET (RS)
with Programmable Flags used in Depth Expansion Configuration
FIRST LOAD (FL)
V
V
CC
CC
D
WEN
D
WCLK
WEN
RS
WCLK
RS
D
WCLK
WEN
RS
FF
FL
FF
FF
FL
FL
7C4282V
7C4292V
7C4282V
7C4292V
7C4282V
7C4292V
14
XO
XO
XO
XI
XI
XI
RCLK
RCLK
RCLK
REN
1. The first device must be designated by grounding the First
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
4. EF and FF composite flags are created by ORing together
REN
OE
REN
OE
OE
EF
EF
EF
Load (FL) control input.
the Expansion In (XI) pin of the next device.
each individual respective flag.
Q
Q
Q
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUTENABLE (OE)
4282V–25
EF
DATA OUT (Q)
CY7C4282V
CY7C4292V