CY7C4282V-10ASC Cypress Semiconductor Corp, CY7C4282V-10ASC Datasheet - Page 6

• Manufacturer Part Number: CY7C4282V-10ASC
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 9 64-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282V-10ASC

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 576 Kb
• Organization: 64Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Switching Waveforms
Read Cycle Timing
Write Cycle Timing
Notes:
10. t
11. t
Q
D
rising edge of RCLK and the rising edge of WCLK is less than t
the rising edge of WCLK and the rising edge of RCLK is less than t
0
0
SKEW1
SKEW1
WCLK
WCLK
RCLK
RCLK
WEN
–D
–Q
WEN
REN
REN
OE
FF
EF
17
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
is also the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
t
[10]
CLKH
CLKH
t
t
t
WFF
A
REF
t
OE
t
t
CLK
CLK
SKEW1
t
SKEW1
NO OPERATION
SKEW2
, then FF may not change state until the next WCLK rising edge.
[11]
t
, then EF may not change state until the next RCLK rising edge.
DS
t
CLKL
t
CLKL
t
ENS
6
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
OHZ
NO OPERATION
CY7C4282V
CY7C4292V
4282V–6
4282V–7