CY7C4282V-10ASC Cypress Semiconductor Corp, CY7C4282V-10ASC Datasheet - Page 3

• Manufacturer Part Number: CY7C4282V-10ASC
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 9 64-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282V-10ASC

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 576 Kb
• Organization: 64Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Pin Definitions
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
Ambient Temperature with
Power Applied
Supply Voltage to Ground Potential
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
Output Current into Outputs (LOW) ............................. 20 mA
D
Q
WEN
REN
WCLK
RCLK
EF
FF
PAE
PAF/XO
FL/RT
XI/LD
OE
RS
Signal Name
0 8
0 8
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full/
Expansion
Output
First Load/
Retransmit
Expansion In-
put/Load
Output Enable
Reset
Description
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Data Inputs for 9-bit bus.
Data Outputs for 9-bit bus.
The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
Enables the device for Read operation. REN must be asserted LOW to allow a Read
operation.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty.
When LD is LOW, RCLK reads data out of the programmable flag-offset register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO. PAE is synchronized to RCLK.
Dual-Mode Pin:
Cascaded - Connected to XI of next device.
Not Cascaded - When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL tied to V
will have FL tied to V
on all devices.
Not Cascaded - Retransmit function is available in stand-alone mode by strobing
RT.
Dual-Mode Pin:
Cascaded - Connected to XO of previous device.
Not Cascaded - LD is used to write or read the programmable flag offset registers. LD
must be asserted LOW during reset to enable standalone or width expansion operation.
If programmable offset register access is not required, LD can be tied to RS directly.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connect-
ed. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
0.5V to V
0.5V to V
0.5V to V
65 C to +150 C
55 C to +125 C
CC
CC
CC
+0.5V
+0.5V
+0.5V
3
CC
. In standard mode or width expansion, FL is tied to V
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Commercial
Industrial
Notes:
1.
2.
T
V
Range
A
CC
is the “instant on” case temperature.
Range for commercial -10 ns is 3.3V ± 150 mV.
[1]
Description
Temperature
0 C to +70 C
40 C to +85 C
Ambient
SS
3.3V / 300mV
3.3V / 300mV
CY7C4282V
CY7C4292V
; all other devices
V
CC
[2]
SS