CY7C4282V-10ASC Cypress Semiconductor Corp, CY7C4282V-10ASC Datasheet - Page 7

• Manufacturer Part Number: CY7C4282V-10ASC
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 9 64-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282V-10ASC

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 576 Kb
• Organization: 64Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Switching Waveforms
REN, WEN
First Data Word Latency after Reset with Simultaneous Read and Write
Reset Timing
Notes:
12. The clocks (RCLK, WCLK) can be free-running during reset.
13. For standalone or width expansion configuration only.
14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
15. When t
16. The first word is available the cycle after EF goes HIGH, always.
Q
D
Q
0
EF,PAE
FF,PAF
0
WCLK
RCLK
0 –
WEN
–D
–Q
REN
The Latency Timing applies only at the Empty Boundary (EF = LOW).
OE
RS
EF
LD
Q
8
8
8
[13]
SKEW1
t
ENS
[12]
> minimum specification, t
t
DS
D
0
(FIRSTVALID WRITE)
(continued)
FRL
t
(maximum) = t
SKEW1
t
t
t
t
RSS
RSF
RSF
RSF
t
RS
t
OLZ
t
FRL
CLK
[15]
+ t
SKEW2
t
REF
D
. When t
1
SKEW1
7
t
OE
< minimum specification, t
t
RSR
t
D
A
2
FRL
(maximum) = either 2*t
D
0
t
A
[16]
D
3
CLK
+ t
OE=0
OE=1
CY7C4282V
CY7C4292V
SKEW1
[14]
or t
CLK
D
+ t
4282V–9
4282V–8
1
SKEW1
D
4
.