PIC18F4680-H/ML Microchip Technology, PIC18F4680-H/ML Datasheet - Page 177

• Manufacturer Part Number: PIC18F4680-H/ML
• Description: IC MCU 8BIT 64KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4680-H/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-VQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.4
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP1 module and offers up to four out-
puts, designated P1A through P1D. Users are also able
to select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the EPWM1M1:EPWM1M0 and
CCP1M3:CCP1M0 bits of the ECCP1CON register.
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the PWM Delay register, ECCP1DEL, which is loaded
at either the duty cycle boundary or the boundary
period (whichever comes first). Because of the buffer-
ing, the module waits until the assigned timer resets
instead of starting immediately. This means that
Enhanced PWM waveforms do not exactly match the
standard PWM waveforms but are instead offset by
one full instruction cycle (4 T
As before, the user must manually configure the
appropriate TRIS bits for output.
FIGURE 16-1:
© 2007 Microchip Technology Inc.
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.
Enhanced PWM Mode
ECCPR1H (Slave)
Duty Cycle Registers
Comparator
ECCPR1L
PR2
TMR2
Comparator
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
(Note 1)
OSC
Clear Timer,
set ECCP1 pin and
latch D.C.
CCP1CON<5:4>
).
R
S
PIC18F2585/2680/4585/4680
EPWM1M1<1:0>
Q
Preliminary
ECCP1DEL
Controller
ECCP1/P1A
Output
16.4.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
EQUATION 16-1:
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The ECCP1 pin is set (if PWM duty cycle = 0%,
• The PWM duty cycle is copied from ECCPR1L
2
the ECCP1 pin will not be set)
into ECCPR1H
Note:
P1C
P1D
P1B
PWM Period =
4
CCP1M<3:0>
PWM PERIOD
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
TRISD<4>
TRISD<5>
TRISD<6>
TRISD<7>
[(PR2) + 1] • 4 • T
(TMR2 Prescale Value)
ECCP1/P1A
P1B
P1C
P1D
DS39625C-page 175
OSC
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