PIC18F4680-H/ML Microchip Technology, PIC18F4680-H/ML Datasheet - Page 329

• Manufacturer Part Number: PIC18F4680-H/ML
• Description: IC MCU 8BIT 64KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4680-H/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-VQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.5.4
In Mode 1 and 2, any of six programmable transmit/
receive buffers may be programmed to automatically
respond to predefined RTR messages without user
firmware intervention. Automatic RTR handling is
enabled by setting the TXnEN bit in the BSEL0 register
and the RTREN bit in the BnCON register. After this
setup, when an RTR request is received, the TXREQ
bit is automatically set and the current buffer content is
automatically queued for transmission as a RTR
response. As with all transmit buffers, once the TXREQ
bit is set, buffer registers become read-only and any
writes to them will be ignored.
The
automatically handle RTR messages:
1.
2.
3.
4.
Normally, user firmware will keep buffer data registers
up to date. If firmware attempts to update the buffer
while an automatic RTR response is in the process of
transmission, all writes to buffers are ignored.
23.6
23.6.1
For the MCU to have write access to the message
buffer, the TXREQ bit must be clear, indicating that the
message buffer is clear of any pending message to be
transmitted. At a minimum, the SIDH, SIDL and DLC
registers must be loaded. If data bytes are present in
the message, the data registers must also be loaded. If
the message is to use extended identifiers, the
EIDH:EIDL registers must also be loaded and the
EXIDE bit set.
To initiate message transmission, the TXREQ bit must
be set for each buffer to be transmitted. When TXREQ
is set, the TXABT, TXLARB and TXERR bits will be
cleared. To successfully complete the transmission,
there must be at least one node with matching baud
rate on the network.
© 2007 Microchip Technology Inc.
Set buffer to Transmit mode by setting TXnEN
bit to
At least one acceptance filter must be
associated with this buffer and preloaded with
expected RTR identifier.
Bit RTREN in BnCON register must be set to
Buffer must be preloaded with the data to be
sent as a RTR response.
following
CAN Message Transmission
‘
1
PROGRAMMABLE AUTO-RTR
BUFFERS
’
INITIATING TRANSMISSION
in BSEL0 register.
outlines
the
steps
required
PIC18F2585/2680/4585/4680
‘
1
Preliminary
’
.
to
Setting the TXREQ bit does not initiate a message
transmission; it merely flags a message buffer as ready
for transmission. Transmission will start when the
device detects that the bus is available. The device will
then begin transmission of the highest priority message
that is ready.
When the transmission has completed successfully, the
TXREQ bit will be cleared, the TXBnIF bit will be set and
an interrupt will be generated if the TXBnIE bit is set.
If the message transmission fails, the TXREQ will remain
set, indicating that the message is still pending for trans-
mission and one of the following condition flags will be
set. If the message started to transmit but encountered
an error condition, the TXERR and the IRXIF bits will be
set and an interrupt will be generated. If the message lost
arbitration, the TXLARB bit will be set.
23.6.2
The MCU can request to abort a message by clearing
the TXREQ bit associated with the corresponding
message buffer (TXBnCON<3> or BnCON<3>). Set-
ting the ABAT bit (CANCON<4>) will request an abort
of all pending messages. If the message has not yet
started transmission, or if the message started but is
interrupted by loss of arbitration or an error, the abort
will be processed. The abort is indicated when the
module sets the TXABT bit for the corresponding buffer
(TXBnCON<6> or BnCON<6>). If the message has
started to transmit, it will attempt to transmit the current
message fully. If the current message is transmitted
fully and is not lost to arbitration or an error, the TXABT
bit will not be set because the message was transmit-
ted successfully. Likewise, if a message is being trans-
mitted during an abort request and the message is lost
to arbitration or an error, the message will not be
retransmitted and the TXABT bit will be set, indicating
that the message was successfully aborted.
Once an abort is requested by setting the ABAT or
TXABT bits, it cannot be cleared to cancel the abort
request. Only CAN module hardware or a POR
condition can clear it.
ABORTING TRANSMISSION
DS39625C-page 327