PIC18F4680-H/ML Microchip Technology, PIC18F4680-H/ML Datasheet - Page 334

• Manufacturer Part Number: PIC18F4680-H/ML
• Description: IC MCU 8BIT 64KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4680-H/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-VQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2585/2680/4585/4680
23.9
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non-Return-
to-Zero (NRZ) coding which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitter’s clock.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the PIC18F2585/2680/4585/4680 is
implemented using a DPLL that is configured to syn-
chronize to the incoming data and provides the nominal
timing for the transmitted data. The DPLL breaks each
bit time into multiple segments made up of minimal
periods of time called the Time Quanta (T
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different clock
frequencies of the individual devices, the bit rate has to
be adjusted by appropriately setting the baud rate
prescaler and number of Time Quanta in each segment.
The Nominal Bit Rate is the number of bits transmitted
per second, assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1 Mb/s.
The Nominal Bit Time is defined as:
EQUATION 23-1:
FIGURE 23-4:
DS39625C-page 332
Input
Signal
Bit
Time
Intervals
T
Baud Rate Setting
Q
T
BIT
= 1/Nominal Bit Rate
Segment
BIT TIME PARTITIONING
Sync
Sync
Propagation
Segment
Q
).
Preliminary
Segment 1
Phase
Nominal Bit Time
The Nominal Bit Time can be thought of as being
divided into separate, non-overlapping time segments.
These segments (Figure 23-4) include:
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 (Phase_Seg2)
The time segments (and thus the Nominal Bit Time) are
in turn made up of integer units of time called Time
Quanta or T
Nominal Bit Time is programmable from a minimum of
8 T
minimum Nominal Bit Time is 1 μs, corresponding to a
maximum 1 Mb/s rate. The actual duration is given by
the following relationship.
EQUATION 23-2:
The Time Quantum is a fixed unit derived from the
oscillator period. It is also defined by the programmable
baud rate prescaler, with integer values from 1 to 64, in
addition to a fixed divide-by-two for clock generation.
Mathematically, this is:
EQUATION 23-3:
where F
corresponding oscillator period and BRP is an integer
(0 through 63) represented by the binary values of
BRGCON1<5:0>. The equation above refers to the
effective clock frequency used by the microcontroller. If,
for example, a 10 MHz crystal in HS mode is used, then
the F
10 MHz crystal is used in HS-PLL mode, then the
effective frequency is F
Nominal Bit Time= T
Q
OSC
to a maximum of 25 T
Sample Point
OSC
T
T
= 10 MHz and T
Q
Q
(μs) = (2 * (BRP + 1))/F
(μs) = (2 * (BRP + 1)) * T
Q
is the clock frequency, T
(see Figure 23-4). By definition, the
Phase_Seg1 + Phase_Seg2)
OSC
Q
© 2007 Microchip Technology Inc.
* (Sync_Seg + Prop_Seg +
Segment 2
or
= 40 MHz and T
Phase
OSC
Q
. Also by definition, the
= 100 ns. If the same
OSC
OSC
(MHz)
(μs)
OSC
OSC
= 25 ns.
is the