PIC18F4680-H/ML Microchip Technology, PIC18F4680-H/ML Datasheet - Page 297

• Manufacturer Part Number: PIC18F4680-H/ML
• Description: IC MCU 8BIT 64KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4680-H/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-VQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE
© 2007 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
[0 ≤ n ≤ 5, TXnEN (BSEL0<n>) = 1]
bit 7
Legend:
R = Readable bit
-n = Value at POR
TXBIF: Transmit Buffer Interrupt Flag bit
1 = A message is successfully transmitted
0 = No message was transmitted
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1 = Requests sending a message; clears the TXABT, TXLARB and TXERR bits
0 = Automatically cleared when the message is successfully sent
RTREN: Automatic Remote Transmission Request Enable bit
1 = When a remote transmission request is received, TXREQ will be automatically set
0 = When a remote transmission request is received, TXREQ will be unaffected
TXPRI1:TXPRI0: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
R/W-0
TXBIF
Note 1: These registers are available in Mode 1 and 2 only.
2: Clearing this bit in software while the bit is set will request a message abort.
3: This bit is automatically cleared when TXREQ is set.
4: While TXREQ is set or transmission is in progress, transmit buffer registers remain
5: These bits set the order in which the transmit buffer will be transferred. They do not
read-only.
alter the CAN message identifier.
TXABT
R-0
PIC18F2585/2680/4585/4680
TXLARB
W = Writable bit
‘1’ = Bit is set
R-0
Preliminary
(2,4)
TXERR
(5)
R-0
(1)
(3)
(3)
(3)
TXREQ
R/W-0
(3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RTREN
R/W-0
x = Bit is unknown
TXPRI1
R/W-0
DS39625C-page 295
TXPRI0
R/W-0
bit 0