SLXT973QC

Manufacturer Part NumberSLXT973QC
ManufacturerCortina Systems Inc
SLXT973QC datasheet
 


Specifications of SLXT973QC

Lead Free Status / Rohs StatusNot Compliant  
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Cortina Systems
Dual-Port Fast Ethernet PHY Transceiver
Datasheet
The Cortina Systems
(LXT973 Transceiver) is an IEEE 802.3 compliant, dual-port, Fast Ethernet PHY
transceiver that directly supports both 100BASE-TX and 10BASE-T applications. Each
port provides a Media Independent Interface (MII) for easy attachment to 10 Mbps and
100 Mbps Media Access Controllers (MACs). The LXT973 Transceiver also provides a
Low-Voltage Positive Emitter Coupled Logic (LVPECL) interface per port for use with
100BASE-FX fiber networks. The LXT973 Transceiver incorporates the auto MDI/MDIX
feature, allowing it to automatically switch twisted-pair inputs and outputs.
The LXT973 Transceiver is an ideal building block for systems that require two Ethernet
ports, such as Internet Protocol (IP) Telephones, Twisted-Pair (TX)-to-Fiber (FX)
converter modules, and for telecom applications, such as Telecom Central Office (TCO)
and Customer Premise Equipment (CPE) devices.
The LXT973 Transceiver supports full-duplex operation at both 10 Mbps and 100 Mbps.
Its operating modes can be set using auto-negotiation, parallel detection, or manual
control.
Applications
Enterprise switches
IP telephony switches
Product Features
Dual-port Fast Ethernet PHY
2.5 Voperation
3.3 Voperation I/O compatibility
Low power consumption; 250 mW per port
typical
Full dual-port MII interface with extended
registers
Auto MDI/MDIX switch over capability
Signal Quality Error (SQE) enable/disable
100BASE-FX fiber-optic capability on both ports
Supports both auto-negotiation systems and
legacy systems without auto-negotiation
capability
Support for Next Page
®
LXT973 10/100 Mbps
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Storage Area Networks
Multi-port Network Interface Cards (NICs)
20 MHz Register Access
Configurable via MDIO port or external control
pins
Integrated termination resistors
100-pin Plastic Quad Flat Package (PQFP)
— Commercial (0
SLXT973QC Transceiver
EGLXT973QC Transceiver (RoHS
Compliant)
°
— (-40
C to +85
SLXT973QE Transceiver
EGLXT973QE Transceiver (RoHS
Compliant
°
°
C to 70
C ambient)
°
C ambient) (Extended)

SLXT973QC Summary of contents

  • Page 1

    ... Storage Area Networks Multi-port Network Interface Cards (NICs) 20 MHz Register Access Configurable via MDIO port or external control pins Integrated termination resistors 100-pin Plastic Quad Flat Package (PQFP) — Commercial (0 SLXT973QC Transceiver EGLXT973QC Transceiver (RoHS Compliant) ° — (- +85 SLXT973QE Transceiver EGLXT973QE Transceiver (RoHS Compliant ° ...

  • Page 2

    ... U.S. and other countries. Other names and brands may be claimed as the property of others. Copyright © 2001−2007 Cortina Systems, Inc. All rights reserved. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Legal Disclaimers ® PRODUCTS. Page 2 ...

  • Page 3

    ... PCS Sublayer ........................................................................................................37 3.8.4 PMA Sublayer ........................................................................................................38 3.8.5 Fiber PMD Sublayer ..............................................................................................39 3.9 10 Mbps Operation .............................................................................................................40 3.9.1 Polarity Correction .................................................................................................40 3.9.2 Dribble Bits ............................................................................................................40 3.9.3 Link Test ................................................................................................................40 3.9.4 Link Failure ............................................................................................................40 3.9.5 Jabber ....................................................................................................................40 3.10 Monitoring Operations ........................................................................................................41 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Contents Page 3 ...

  • Page 4

    ... Dribble Bits .........................................................................................................................62 10.7 Transmit Polarity Control ....................................................................................................62 10.8 PHY Address ......................................................................................................................62 11.0 Clock Generation .........................................................................................................................63 11.1 External Oscillator...............................................................................................................63 12.0 Register Definitions.....................................................................................................................65 13.0 Magnetics Information ................................................................................................................75 14.0 Test Specifications......................................................................................................................76 15.0 Timing Diagrams .........................................................................................................................81 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Contents Page 4 ...

  • Page 5

    ... LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 16.0 Mechanical Specifications ..........................................................................................................92 16.1 Top Label Marking ..............................................................................................................92 17.0 Product Ordering Information ....................................................................................................95 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Contents Page 5 ...

  • Page 6

    ... MII - 10BASE-T Transmit Timing Parameters (Parallel Mode)......................................................85 45 MII - 10BASE-T Receive Timing Parameters (Parallel Mode).......................................................86 46 10BASE-T SQE (Heartbeat) Timing Parameters ..........................................................................87 47 10BASE-T Jab and Unjab Timing Parameters ..............................................................................87 48 Fast Link Pulse Timing Parameters...............................................................................................88 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 2...............................................................................................................................77 Tables Page 6 ...

  • Page 7

    ... LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 49 MDIO Timing Parameters ..............................................................................................................89 50 Power-Up Timing Parameters .......................................................................................................90 51 RESET Pulse Width and Recovery Timing Parameters ................................................................91 52 Product Ordering Information ........................................................................................................95 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Tables Page 7 ...

  • Page 8

    ... Example of Top Marking Information Labeled as Cortina Systems, Inc. .......................................93 45 Sample PQFP Package (marked as Intel*) – LXT973QC Transceiver .........................................93 46 Sample Pb-Free (RoHS-Compliant) PQFP Package (marked as Intel*) – * Intel EGLX973QC Transceiver ..................................................................................................94 47 Ordering Information – Sample .....................................................................................................96 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figures Page 8 ...

  • Page 9

    ... Modified text under Section 4.1.7, “Magnetics Replaced Figure 14 “Recommended LXT973-to-3.3 VFiber Transceiver Interface ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Revision 6.0 Revision Date: 13 July 2007 Revision 5.0 Revision Date: 06 July 2007 Revision#: 004 Revision Date: 29 November 2005 95 ...

  • Page 10

    ... Pins”. Modified Table 40 on page 77 through Table 49 on page ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Revision Number: 003 Revision Date: 20 January 2004 Circuitry”. Translator”. Section 9.0, “Fiber Interface”. (changed ”hardware pins” to “FIBER_TPn”. ...

  • Page 11

    ... Information”: Added product ordering information table and diagram. Initial Release (Preliminary datasheet) ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Revision Number: 002 Revision Date: June 2002 Parameters”. and Table 51 “RESET Pulse Width and Recovery Timing ...

  • Page 12

    ... Data Valid COLn Error Detect CRSn See Table 4, Network Interface Signal Descriptions, on page 19 Note: Descriptions, on page 20 for complete network interface signal configurations. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Dual-Port Global Functions Clock Generator + Manchester 10 TP Encoder Pulse ...

  • Page 13

    ... SGND REFCLK GNDD FIBER_TP1 FIBER_TP0 MDDIS1 MDDIS0 PWRDWN1 MDC1 MDIO1 PWRDWN0 MDIO0 MDC0 VCCIO GNDIO RXD0_3 RXD0_2 Package Topside Markings Marking Part # Rev # Lot # FPO # ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver LXT973QE XX Part # 18 FPO # XXXXXXXX 19 20 ...

  • Page 14

    ... AI = Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-down. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1.0 Pin Assignments and Signal Reference for Full 1 Type Description ...

  • Page 15

    ... AI = Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-down. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1.0 Pin Assignments and Signal Reference for Full 1 Type Description ...

  • Page 16

    ... AI = Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-down. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1.0 Pin Assignments and Signal Reference for Full 1 Type Description ...

  • Page 17

    ... AI = Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-down. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Type Signal Description Transmit Data. TXD0_ bundle of parallel data signals driven by the MAC controller, which TXD0< ...

  • Page 18

    ... AI = Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-Down ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Type Signal Description Management Disable. When MDDIS0 is tied High, the MDIO port is completely disabled and the Hardware Control Interface pins set their respective bits at power-up and reset ...

  • Page 19

    ... AI = Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-Down ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Type Signal Description Collision Detected. The LXT973 Transceiver asserts this output when a collision is detected ...

  • Page 20

    ... Reset. This active Low input is OR’d with Control Register bit 0.15. Address <4:1>. Sets device Port 0 PHY address. Note that ADDR0 is set internally so that Port 1 is always “1” address higher than Port 0. ...

  • Page 21

    ... AI = Analog Input Analog Output Input Output Open Drain output Schmitt Triggered input Three-State-able output Slew-rate Limited output Weak Internal Pull-up Weak Internal Pull-Down ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Type Signal Description – Digital Power Supply - Core. +2.5 V supply for core digital circuits. ...

  • Page 22

    ... Duplex. Sets the duplex setting of the port in Hardware mode. High is full-duplex and Low is half-duplex Fiber/Twisted-Pair. Sets the operating state of the port in Hardware mode. High is twisted-pair and Low is fiber. I Power-Down. When set High, this pin puts the relevant PHY into I power-down mode. 2.0 Signal Descriptions Page 22 ...

  • Page 23

    ... Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT973 Transceiver automatically detects (parallel detection) the presence of either link pulses (10 Mbps PHY) or IDLE symbols (100 Mbps PHY) and sets its operating conditions accordingly. When parallel detection is used to establish link, the resulting link is at half- duplex ...

  • Page 24

    ... When not transmitting data, the LXT973 Transceiver generates “IDLE” symbols. During 10 Mbps operation, LXT973 Transceiver encoded data is exchanged. When no data is exchanged, the line transmits normal link pulses to maintain link. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.2 Interface Descriptions TXENn TXDn<3:0> TXERn ...

  • Page 25

    ... For 100BASE-TX links, RXDV is asserted from the first nibble of preamble to the last nibble of the data packet. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 56. Default mode is auto-MDIX enabled. 3.3 MII Operation Section Page 25 ...

  • Page 26

    ... During test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT973 Transceiver and returned to the MAC (see Figure 4). ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver summarizes the conditions for assertion of carrier Figure 4 on page 27. 3.3 MII Operation Page 26 ...

  • Page 27

    ... Test loopback is enabled when Register bit 0. Register bit 0 and Register bit 0. 3.3.8 Configuration Management Interface The LXT973 Transceiver provides an MDIO Management Interface and a Hardware Control Interface for device configuration and management. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Digital Analog 10T 100X Block Block ...

  • Page 28

    ... LXT973 Transceiver. The MDIO interface consists of a physical connection, a specific protocol which runs across the connection, and an internal set of addressable registers. The physical interface consists of a data line (MDIO) and clock line (MDC), and a control line (MDDIS). The maximum speed of MDC is 20 MHz ...

  • Page 29

    ... V or +3.3 V. VCCIO should be supplied from the same power source used to supply the controller on the other side of the interface matter of good practice, these supplies should be as clean as possible. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver BASE ADDR<4.1> Example ADDR<4.1> = 0001 Port Port LXT973 PHY ADDR< ...

  • Page 30

    ... In general, an oscillator-based clock source is recommended over a derived clock due to frequency stability and overall signal integrity. Regardless of clock source, careful consideration should be given to physical placement, board layout, and signal routing of the source to maintain the highest possible level of signal integrity ...

  • Page 31

    ... All the MII interface pins are disabled during a hardware reset and released to the bus on de-assertion of reset. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 16 on page 66). During individual port power-down, the Table 9 on page 32 for pin settings and 3 ...

  • Page 32

    ... High Low High Low High Low 1. These pins also set the default values for Registers 0 and 4 accordingly. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver SPEEDx DUPLEXx 100BASE-FX is enabled in half-duplex mode. - Low Auto-negotiation is disabled. 100BASE-FX is enabled in full-duplex mode. - High Auto-negotiation is disabled ...

  • Page 33

    ... In 10 Mbps mode, link is established based on the link state machine found in the IEEE 802.3, Clause 14.X specification. Receiving 100 Mbps idle patterns does not bring Mbps link. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.6 Link Establishment Page 33 ...

  • Page 34

    ... IEEE 802.3-compliant link pulses or an IDLE code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending on the mode selected. Auto- negotiation/parallel detection or manual control is used to determine the speed of this interface. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Power-Up, Reset, Link Failure Start 0. 0. ...

  • Page 35

    ... The LXT973 Transceiver supports two fault detection and reporting mechanisms. “Remote Fault” refers to a MAC-to-MAC communication function that is essentially transparent to PHY layer devices, and is used only during auto-negotiation. Therefore, Remote Fault is applicable only to twisted-pair links. "Far End Fault" optional PMA- layer function that may be embedded within PHY devices ...

  • Page 36

    ... Replaced by Start-of-Frame /J/K/ code-groups Delimiter (SFD) Start-of-Stream Delimiter (SSD) ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 9 shows the structure of a standard frame packet. Destination and Source Packet Length Data Field Address (6 Octets each) (2 Octets) (Pad to minimum packet size) ...

  • Page 37

    ... PCS Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TXEN is de-asserted. For 10BASE-T operation, the PCS layer merely provides a bus interface and serialization/ de-serialization function ...

  • Page 38

    ... Frame is asserted for one clock cycle when CRS is de-asserted. 3.8.4.3 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3), as well as receiving, polarity correction, and baseline wander correction functions. ® ...

  • Page 39

    ... Sublayer to stop and the Far End fault code to begin. The Far End Fault code consists of 84 “1s” followed by a single “0”, and is repeated until the Far End Fault condition is removed. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.8 100 Mbps Operation Page 39 ...

  • Page 40

    ... If a transmission exceeds the jabber timer, the LXT973 Transceiver disables the transmit and loopback functions. The LXT973 Transceiver automatically exits jabber mode after the unjab time has expired. This function is disabled by setting Register bit 16. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 3.9 10 Mbps Operation Page 40 ...

  • Page 41

    ... LED configurations for the LXT973 Transceiver. Table 10 LED Configurations LED_CFG0 LED_CFG1 Figure 11 Typical LED Implementation ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Table 17 on page 67). Table 10 on page Figure 11 LEDn_1 LEDn_2 Speed Link 0 Speed Link/Activity Link Receive 1 ...

  • Page 42

    ... LXT973 Transceiver, helping with line performance. Second, if the VCC planes are laid out correctly, digital switching noise is kept away from external connectors, reducing EMI problems. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 4.0 Application Information Page 42 ...

  • Page 43

    ... Please refer to the LXT973 Transceiver Design and Layout Guide for series resistor values. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver F) should be placed on each side of each bead. In addition, a μ F) should be placed near each analog VCC pin. ...

  • Page 44

    ... LXT973 Transceiver. See the 100BASE-FX Fiber Optic Transceivers- Connecting a PECL/LVPECL Interface Application Note (document number 250781) for detailed information on fiber interface designs and recommendations for Cortina PHYs. The following should occur in 3.3 V fiber transceiver applications as shown in • The transmit pair should be AC-coupled with 2.5 V supplies and re-biased to 3.3 VLVPECL levels • ...

  • Page 45

    ... Transformer isolation Differential to common mode rejection -16 Return Loss -10 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Figure 13 on page 47). When using the auto MDI/MDIX for transformer requirements. Before committing to a specific Nom Max Units Test Condition – 1:1 – ...

  • Page 46

    ... VCCR/VCCT LXT973 VCCD GNDD VCCIO VCCPECL GNDPECL ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 4.2 Typical Application Circuits show typical application circuits for the 0.01 μF Analog Supply Plane Ferrite Bead Digital Supply Plane 0.01 μF 0.01 μF 10 μ ...

  • Page 47

    ... Port 1 LXT973 1. The 100 Ω transmit load termination resistor typically required is integrated in the LXT973 Transceiver. 2. The 100 Ω receive load termination resistor typically required is integrated in the LXT973 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver DPAP_0 1 DPAN_0 DPBP_0 ...

  • Page 48

    ... DPBPn LXT973 SDn DPANn DPAPn SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver +3.3 V +2.5 V 0.01 μ Ω 1.4 kΩ 0.1 μF 0 Ω 50 Ω 0.01 μF 0.01 μ ...

  • Page 49

    ... DPANn DPAPn SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. 2. See Figure 16 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver +5 V +2.5 V 0.01 μ Ω 0.1 μF 1.15 kΩ 1.1 kΩ 50 Ω 50 Ω 0.01 μF 0.01 μ ...

  • Page 50

    ... Revision 6.0 13 July 2007 Figure 16 ON Semiconductor* Triple PECL-to-LVPECL Logic Translator 0.01 μ Ω PECL Input Signal 130 Ω Fiber Txcvr) Figure 17 Typical MII Interface MAC ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Semiconductor* Vcc Vcc ...

  • Page 51

    ... In the Manual Control Mode, LXT973 Transceiver disables direct write operations to the MDIO registers on the MDIO interface. The Hardware Control Interface is monitored during Reset to set up the MDIO registers. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 4.3 Initialization Table 12 Page 51 ...

  • Page 52

    ... July 2007 Figure 18 Initialization Sequence Table 12 Mode Control Settings MDDISn Low High - - ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Power-up or Reset Read H/W Control Interface Initialize MDIO Registers MDIO Control Mode MDDISn = 0 MDDIS Pass Control to MDIO Interface RESET ...

  • Page 53

    ... High High High High Low 1. These pins also set the default values for Registers 0 and 4 accordingly. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver SPEEDx DUPLEXx 100BASE-FX is enabled in half-duplex mode. – Low Auto-negotiation is disabled 100BASE-FX is enabled in full-duplex mode. ...

  • Page 54

    ... High Low High Low 1. These pins also set the default values for Registers 0 and 4 accordingly. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver SPEEDx DUPLEXx AUTO_NEG is disabled. LXT973 Transceiver port High Low x is forced to 100 Mbps half-duplex operation. ...

  • Page 55

    ... July 2007 6.0 Auto Negotiation The LXT973 Transceiver PHY supports the IEEE 802.3u auto-negotiation scheme with Next Page capability. Next Page exchange utilizes Register 7 to send information and Register 8 to receive them. Next Page exchange can only occur if both ends of the link advertise their ability to exchange Next Pages ...

  • Page 56

    ... PHY-dependent data. If link pulses or PHY-dependent data are detected, it remains in that configuration. If link pulses or PHY-dependent data are not detected, it increments its LFSR and makes a decision to switch based on the value of the next bit. ...

  • Page 57

    ... Displaying Symbol Errors The PHY provides the MAC with an indication of errors that occur during the receive process. This output is called RXER possible to map the symbol error detection output to the RXER pin using Register bit 26.9. In normal mode (Register bit 26.9 = 0), the RXER output is active per the IEEE 802 ...

  • Page 58

    ... Once the transmit data (or IDLE symbols) are properly encoded, they are scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed. Five-seed bits are determined by global PHY address, and six-seed bits are selected by the port number. One of the 11 bits must be a “1”. ...

  • Page 59

    ... Reception with Invalid Symbol RXCLK RXDV RXD<3:0> preamble SFD SFD DA RXER Figure 23 100BASE-TX Transmission with no Errors TXCLK TXEN TXD<3:0> P CRS COL Figure 24 100BASE-TX Transmission with Collision TXCLK TXEN TXD<3:0> P CRS COL ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver JAM JAM 8 ...

  • Page 60

    ... A register bit has been provided that either selects normal, unscrambled fiber data, or scrambles the transmitted fiber data (Register bit 26.10). When in loopback mode, the remote fault condition is not transmitted. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 9.0 Fiber Interface Page 60 ...

  • Page 61

    ... If link pulses or data are not received for 96-130 ms, the polarity state is reset to a non-inverted state. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 10.0 10 Mbps Operation Figure 35 on page 87 for SQE timing parameters. Figure 36 on page 87 ...

  • Page 62

    ... PHY Address 10.8 The LXT973 Transceiver provides four bits to set the PHY address.The least significant bit is fixed internally with Port 1 always being one address higher than Port 0. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 10 ...

  • Page 63

    ... REFCLK (25 MHz Oscillator Clock) ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver illustrate the different frequencies of clock for 2.5 MHz Clock During Auto-Negotiation and 10BASE-T Data / Idle 2.5 MHz Clock During Auto-Negotiation and 10BASE-T Data / Idle 11.0 Clock Generation ...

  • Page 64

    ... Figure 27 Link Down Clock Transition RXCLK TXCLK ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Link Down condition/Auto Negotiate Link Up Any Clock 2.5 MHz Clock Clock transition time will not exceed 2.5x the destination clock period. 11.1 External Oscillator ...

  • Page 65

    ... Base Registers 0 through 8 are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-Negotiation” sections of the IEEE 802.3 specification. Additional registers are defined in accordance with the IEEE 802.3 specification for adding unique chip functions ...

  • Page 66

    ... The Isolate function (Register bit 0.10) three-states all port MAC interface outputs. On the input side, TXEN and TXER are ignored. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Description 1 = PHY reset 0 = Normal operation 1 = Enable loopback mode 0 = Disable loopback mode 0 ...

  • Page 67

    ... PHY able to operate at 10 Mbps in full-duplex 1 = mode PHY not able to operate at 10 Mbps full-duplex 0 = mode PHY able to operate at 10 Mbps in half-duplex 1 = mode PHY not able to operate at 10 Mbps in half duplex PHY able to perform full-duplex 100BASE- PHY not able to perform full-duplex 100BASE PHY able to perform half-duplex 100BASE-T2 ...

  • Page 68

    ... Manufacturer’s 3.3:0 revision number 1. Refer to Table 15 on page 65 Figure 28 PHY Identifier Bit Mapping Organizationally Unique Identifier PHY ID Register #1 (address 2) = 0013 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Description The PHY identifier composed of bits 3 through 18 of the OUI for Register Bit Descriptions ...

  • Page 69

    ... Register bits 4.10 and 4.8:5 are initialized based on the pin configuration value. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Description 1 = PHY is capable of Next Page exchanges 0 = PHY is not capable of Next Page exchanges Write as 0, ignore on read 1 = Remote fault remote fault. Write as 0, ignore on read Pause operation defined in Clause 40 and 27 Pause operation defined per IEEE 802 ...

  • Page 70

    ... Per IEEE revised standard November 1997, this register is no longer used to store Link Partner Next Note: Pages. Register 8 is now used for this purpose. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Description 1 = Link Partner has ability to send multiple pages Link Partner has no ability to send multiple pages ...

  • Page 71

    ... Refer to Table 15 on page 65 2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read. This table contains modifications that are selectable in Cortina PHYs. These modifications are used Note: to ease the implementation of software Next Page. See separate Cortina tutorial/white-paper on the usage of Next Pages. ® ...

  • Page 72

    ... Message/Unformatted 8.10:0 Code Field 1. Refer to Table 15 on page 65 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Description 1 = Additional Next Pages follow 0 = Last page Write as 0, ignore on read 1 = Message Page 0 = Unformatted page 1 = Complies with message 0 = Does not comply with message ...

  • Page 73

    ... Fiber Select 1. Refer to Table 15 on page 65 2. Register bit 16.0 is latched in from FIBER_TPn on hardware reset. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Description Write as 0, ignore on read 1 = Force Link pass (sets appropriate registers and LEDs to pass Normal operation ...

  • Page 74

    ... Detected 27.3:0 Reserved 1. Refer to Table 15 on page 65 2. Register bits 27.11:10 are latched in from hardware pins on hardware reset. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Description 111 = Longest Approximate line- 110 = length corresponding to 101 = each value will be ...

  • Page 75

    ... Parameter Turns Ratio Insertion Loss Primary Inductance Transformer Isolation Differential to common mode rejection Return Loss Rise Time ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 13.0 Magnetics Information Min Nom Max Units – 1:1, 1:1 – – 0.0 – ...

  • Page 76

    ... V D (digital core VCCIO = digital I/O ring VCCPECL = PECL supply for fiber ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver through Table 51 on page 91 and Figure 29 on page 81 represent the performance specifications of the LXT973 Table 30 on page 77 Sym ...

  • Page 77

    ... Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. 2. For 2.5 V operation, SD_2P5V = VCCPECL and VCCPECL=2 For 3.3 V operation, SD_2P5V = GNDPECL or Floating and VCCPECL=3.3 V. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Sym Min – ...

  • Page 78

    ... Output High Current Input Leakage Current 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Symbol Min Typ Max V – ...

  • Page 79

    ... IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. 4. After line model specified by IEEE 802.3 for 10BASE-T MAU. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Sym Min Typ ...

  • Page 80

    ... Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 1 Sym Min Typ ...

  • Page 81

    ... TXEN sampled to twisted-pair output (Tx latency) 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver refer to MII timings. 0ns ...

  • Page 82

    ... Receive start of “T” to COL de- asserted 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 0ns Input t4 CRS t3 RXDV ...

  • Page 83

    ... TXEN sampled to CRS de- asserted TXEN sampled to fiber output (Tx latency) 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 0ns 250ns ...

  • Page 84

    ... Receive start of “T” to COL de- asserted 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 0ns 250ns Sym ...

  • Page 85

    ... TXEN sampled to CRS asserted TXEN sampled to CRS de-asserted TXEN sampled to twisted-pair output (Tx latency) 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver ...

  • Page 86

    ... Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. 2. CRS is asserted. RXD/RXDV are driven at the start of SFD (64 BT) unless Register bit 16.5 is set Register bit 16.7 is set, CRS extends to RXDV de-assert. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver ...

  • Page 87

    ... Jab and Unjab Timing Parameters Parameter Maximum transmit time Unjab time 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Sym Min ...

  • Page 88

    ... FLP burst to FLP burst Clock/Data pulses per burst 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Clock Pulse Data Pulse ...

  • Page 89

    ... Parameter MDIO setup before MDC 1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to production testing. 2. When operated at 2.5 MHz. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Sym ...

  • Page 90

    ... Power-up delay is specified as a maximum value because it refers to the guaranteed performance of the PHY. The PHY comes out of reset after a delay of no more than 300 μ S. System designers should consider this as a minimum value. After threshold 300 μ S before accessing the MDIO port. ...

  • Page 91

    ... Reset recovery delay is specified as a maximum value because it refers to the PHY’s guaranteed performance. - the PHY comes out of reset after a delay of no more than 300 μ S. System designers should consider this as a minimum value. After de-asserting RESET, the MAC should delay no less than 300 μ ...

  • Page 92

    ... Further information regarding RoHS and lead-free components can be obtained from your local Cortina representative. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver 100-Pin Plastic Quad Flat Pack • Part Number: LXT973QC & LXT973QE • Temperature Range: — Commercial: 0° to 70°C & ...

  • Page 93

    ... Country of Origin Figure 45 Sample PQFP Package (marked as Intel*) – LXT973QC Transceiver Figure 46 shows a sample Pb-free RoHS-compliant PQFP package for the LXT973 Transceiver. ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Device Name FPO Traceability Code Pin 1 LXT973QC A3 XXXXXXXX BSMC FV 16 ...

  • Page 94

    ... Datasheet 249426, Revision 6.0 13 July 2007 Figure 46 Sample Pb-Free (RoHS-Compliant) PQFP Package (marked as Intel*) – * Intel EGLX973QC Transceiver ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Pin 1 EGLXT973C A3 XXXXXXXX e3 BSMC FV 16.1 Top Label Marking Part Number FPO Number ...

  • Page 95

    ... July 2007 17.0 Product Ordering Information Table 52 lists the LXT973 Transceiver product ordering information. the ordering information matrix. Table 52 Product Ordering Information Number SLXT973QC.A3V EGLXT973QC.A3V SLXT973QE.A3V EGLXT973QE.A3V ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Revision Package Type ...

  • Page 96

    ... LXT973 Transceiver Datasheet 249426, Revision 6.0 13 July 2007 Figure 47 Ordering Information – Sample S LXT 973 ® Cortina Systems LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Product Revision Alphanumeric characters Temperature Range A = Ambient (0 – Commercial (0 – Extended (-40 – 85 Internal Package Designator ...

  • Page 97

    For additional product and ordering information: www.cortina-systems.com ~ End of Document ~ TM ...