SC16C850IBS,157 NXP Semiconductors, SC16C850IBS,157 Datasheet - Page 23

• Manufacturer Part Number: SC16C850IBS,157
• Description: IC UART SGL W/FIFO 32HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850IBS,157

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 2.5 V ~ 3.3 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
SC16C850
Product data sheet
7.1 Transmit (THR) and Receive (RHR) Holding Registers
7.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
transmit FIFO. The THR empty flag in the LSR will be set to a logic 1 when the transmit
FIFO is empty or when data is transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C850
receive FIFO by reading the RHR. The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start bit, an internal receiver counter
starts counting clocks at the 16× clock rate. After 7
shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a
logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INT output pin.
Table 9.
Bit
7
6
5
4
3
2
Symbol Description
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
IER[2]
Interrupt Enable Register bits description
All information provided in this document is subject to legal disclaimers.
CTS interrupt.
RTS interrupt.
Xoff interrupt.
Sleep mode.
Modem Status Interrupt. This interrupt will be issued whenever there is a modem
status change as reflected in MSR[3:0].
Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C850 issues an interrupt when
the CTS pin transitions from a logic 0 to a logic 1.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C850 issues an interrupt when
the RTS pin transitions from a logic 0 to a logic 1.
logic 0 = disable the software flow control, receive Xoff interrupt (normal default
condition)
logic 1 = enable the receive Xoff interrupt
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
logic 0 = disable the modem status register interrupt (normal default condition)
logic 1 = enable the modem status register interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 2 — 11 November 2010
1
⁄
2
clocks, the start bit time should be
SC16C850
© NXP B.V. 2010. All rights reserved.
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