SC16C852VIET,118 NXP Semiconductors, SC16C852VIET,118 Datasheet - Page 37

• Manufacturer Part Number: SC16C852VIET,118
• Description: IC UART DUAL W/FIFO 36TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIET,118

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
SC16C852_1
Product data sheet
7.17 Flow Control Trigger Level High (FLWCNTH)
7.18 Flow Control Trigger Level Low (FLWCNTL)
7.19 Clock Prescaler (CLKPRES)
[1]
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
bit settings; see
Table 29.
[1]
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
settings; see
Table 30.
[1]
This register hold values for the clock prescaler.
Table 31.
Bit
7:0
Bit
7:0
Bit
7:4
3:0
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
Symbol
FLWCNTH[7:0]
Symbol
FLWCNTL[7:0]
Symbol
CLKPRES[7:4]
CLKPRES[3:0]
FLWCNTH register bits description
FLWCNTL register bits description
Clock Prescaler register bits description
Section
Section
6.5.
Rev. 01 — 31 August 2009
6.5.
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
Description
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode
Description
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode
Description
reserved
Clock Prescaler value. Reset to 0.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Section
Section
Section
7.3.
7.3.
7.3.
Table 30
Table 29
shows FLWCNTL register bit
shows FLWCNTH register
SC16C852
© NXP B.V. 2009. All rights reserved.
[1]
[1]
37 of 60
.
.