SC16C852VIET,118 NXP Semiconductors, SC16C852VIET,118 Datasheet - Page 9

• Manufacturer Part Number: SC16C852VIET,118
• Description: IC UART DUAL W/FIFO 36TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIET,118

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 2.
[1]
SC16C852_1
Product data sheet
Symbol
TXA
TXB
TXRDYA
TXRDYB
V
V
XTAL1
XTAL2
LOWPWR 12
16/68
n.c.
DD
SS
HVQFN32 package die supply ground is connected to both V
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
Pin description
Pin
LQFP48
7
8
43
6
42
17
13
14
24
25, 37
HVQFN32
5
6
-
-
26
13
10
11
9
17
-
[1]
…continued
Type
O
O
O
O
I
I
I
O
I
I
-
Description
Transmit data A, B. These outputs are associated with individual serial
transmit channel data from the SC16C852. The TX signal will be a logic 1
during reset, idle (no data), or when the transmitter is disabled. During the local
loopback mode, the TXA/TXB output pin is disabled and TX data is internally
connected to the UART RX input.
Transmit Ready A, B (active LOW). These outputs provide the TX FIFO/THR
status for individual transmit channels (A to B). TXRDY is primarily intended for
monitoring DMA mode 1 transfers for the transmit data FIFOs. An individual
channel’s TXRDYA, TXRDYB buffer ready status is indicated by logic 0, that is,
at lease one location is empty and available in the FIFO or THR. This pin goes
to a logic 1 (DMA mode 1) when there are no more empty locations in the FIFO
or THR. This signal can also be used for single mode transfers (DMA mode 0).
Power supply input.
Signal and power ground.
Crystal or external clock input. Functions as a crystal input or as an external
clock input. A crystal can be connected between this pin and XTAL2 to form an
internal oscillator circuit. Alternatively, an external clock can be connected to
this pin to provide custom data rates (see
generator”). See
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal
oscillator output or buffered clock output. Should be left open if an external
clock is connected to XTAL1.
Low Power. When asserted (active HIGH), the device immediately goes into
low power mode. The oscillator is shut-off and some host interface pins are
isolated from the host’s bus to reduce power consumption. The device only
returns to normal mode when the LOWPWR pin is de-asserted. On the
negative edge of a de-asserting LOWPWR signal, the device is automatically
reset and all registers return to their default reset states. This pin has an
internal pull-down resistor, therefore, it can be left unconnected.
Bus select. Intel or Motorola bus select.
When 16/68 pin is at logic 1 or left unconnected (internally pulled-up) the
device will operate in Intel bus type of interface.
When 16/68 pin is at logic 0, the device will operate in Motorola bus type of
interface.
not connected
Rev. 01 — 31 August 2009
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
SS
pin and exposed center pad. V
Figure
6.
Section 6.9 “Programmable baud rate
SS
pin must be connected to supply
SC16C852
© NXP B.V. 2009. All rights reserved.
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