SC16C852VIET,118 NXP Semiconductors, SC16C852VIET,118 Datasheet - Page 43

• Manufacturer Part Number: SC16C852VIET,118
• Description: IC UART DUAL W/FIFO 36TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIET,118

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 40.
T
[1]
[2]
[3]
[4]
SC16C852_1
Product data sheet
Symbol
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
N
WH
WL
w(clk)
XTAL1
su(A)
h(A)
su(RWL-CSL)
su(RWH-CSL)
w(CS)
d(CS)
d(CS-Q)
dis(CS-QZ)
h(CS-RWH)
d(RW)
su(D-CSH)
h(CSH-D)
d(modem-IRQL)
d(CS-IRQH)R
d(stop-IRQL)
d(CS-TX)W
d(start-IRQL)
d(CS-IRQH)W
d(CS-Q)W
w(RESET_N)
amb
Applies to external clock, crystal oscillator max 24 MHz.
Maximum frequency =
1 k pull-up resistor on IRQ pin.
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
= 40 C to +85 C; tolerance of V
Dynamic characteristics - Motorola or 68 mode
Parameter
pulse width HIGH
pulse width LOW
clock pulse width
frequency on pin XTAL1
address set-up time
address hold time
set-up time from R/W LOW to CS LOW
set-up time from R/W HIGH to CS LOW
CS pulse width
CS delay time
delay time from CS to data output
disable time from CS to high-impedance
data output
hold time from CS to R/W HIGH
R/W delay time
set-up time from data input to CS HIGH
data input hold time after CS HIGH
delay time from modem to IRQ LOW
read delay time from CS to IRQ HIGH
delay time from stop to IRQ LOW
write delay time from CS to TX
delay time from start to IRQ LOW
write delay time from CS to IRQ HIGH
write delay time from CS to data output
pulse width on pin RESET
baud rate divisor
-------------- -
t
w clk
1
DD
10 %; unless otherwise specified.
Rev. 01 — 31 August 2009
Dual UART with 128-byte FIFOs and IrDA encoder/decoder
Conditions
25 pF load
25 pF load
25 pF load
25 pF load
[1][2]
[3][4]
[3]
[3]
[4]
[4]
[3]
8T
12.5
Min
10
15
10
10
50
20
10
10
15
15
10
RCLK
V
6
6
1
-
-
-
-
-
-
-
-
-
DD
= 2.5 V
24T
(2
1T
1T
Max
16
80
50
20
40
40
55
40
RCLK
RCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
RCLK
-
1)
8T
12.5
SC16C852
Min
10
15
10
10
20
10
10
10
15
15
10
RCLK
V
6
6
1
-
-
-
-
-
-
-
-
-
DD
© NXP B.V. 2009. All rights reserved.
= 3.3 V
24T
(2
1T
1T
Max
16
80
20
20
30
30
45
33
RCLK
RCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RCLK
1)
43 of 60
Unit
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
ns
ns
ns