A62S6308X-70SI AMIC Technology Corporation, A62S6308X-70SI Datasheet
A62S6308X-70SI
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A62S6308X-70SI Summary of contents
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Document Title 64K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History 1.0 Initial issue 1.1 Modify TSOP (TSSOP) pin configuration. Modify SOP 32L, TSOP 32L and TSSOP 32L type packages outline dimensions. 1.2 Change TSSOP 32L ...
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... Data retention is guaranteed at a power supply voltage as low as 2V TSOP/(sTSOP) (forward type A62S6308V 8 25 (A62S6308X A62S6308 Series n n Mini BGA (6X8) Top View 1 2 ...
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Block Diagram A0 A13 A14 A15 I/O 1 I/O 8 CE2 CE1 CONTROL CIRCUIT OE WE Pin Descriptions - SOP Pin No. Symbol 1 Connection 3 - 12, 23 A15 Address Inputs 25 - 28, 31 ...
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Recommended DC Operating Conditions ( - Symbol Parameter VCC Supply Voltage GND Ground V Input High Voltage IH V Input Low Voltage IL C Output Load L TTL ...
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DC Electrical Characteristics (continued) Symbol Parameter I SB Standby Power I SB1 Supply Current I SB2 V Output Low Voltage OL V Output High Voltage OH Truth Table Mode CE1 H Standby X Output Disable L Read L Write L ...
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AC Characteristics ( - VCC = 2.7V to 3.6V) A Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t ACE1 Chip Enable ...
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Timing Waveforms ( Read Cycle 1 Address D OUT ( Read Cycle 2 CE1 CLZ1 OUT ( ,8) Read Cycle 3 CE2 CLZ2 OUT (October, 1998, Version ...
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Timing Waveforms (continued) (1) Read Cycle 4 Address OE CE1 CE2 D OUT Notes high for Read Cycle. 2. Device is continuously enabled CE1 = V 3. Address valid prior to or coincident with CE1 transition low. ...
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Timing Waveforms (continued) (6) Write Cycle 1 (Write Enable Controlled) Address CE1 CE2 OUT (October, 1998, Version 2. (4) ( ...
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Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) Address CE1 CE2 OUT Notes measured from the address valid to the beginning of Write Write occurs during the overlap (t ...
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AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Including scope and jig. Figure 1. Output Load Data Retention Characteristics Symbol Parameter V DR1 VCC for Data ...
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Low VCC Data Retention Waveform (1) ( CE1 Controlled) VCC 2.7V t CDR V CE1 IH Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC 2.7V t CDR CE2 V IL (October, 1998, Version 2.0) DATA RETENTION MODE V 2V ...
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... Ordering Information Access Time (ns) Part No. A62S6308M-70S A62S6308M-70SI A62S6308V-70S A62S6308V-70SI A62S6308X-70S A62S6308X-70SI A62S6308G-70S A62S6308G-70SI A62S6308M-10S A62S6308M-10SI A62S6308V-10S A62S6308V-10SI A62S6308X-10S A62S6308X-10SI A62S6308G-10S A62S6308G-10SI (October, 1998, Version 2.0) Operating Current Max. (mA 100 A62S6308 Series Standby Current Package Max ...
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Package Information SOP (W.B.) 32L Outline Dimensions Seating Plane Symbol Notes: 1. The maximum value of dimension D ...
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Package Information TSOP 32L TYPE 20mm) Outline Dimensions y Symbol Notes: 1. The maximum value of dimension D includes end ...
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Package Information sTSOP 32L TYPE 13.4mm) Outline Dimensions 0.076MM SEATING PLANE Symbol Notes: 1. The maximum value of dimension D 2. ...
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Package Information Mini BGA 6X8 (36 BALLS) Outline Dimensions Bottom View (October, 1998, Version 2.0) Pin A1 Index Pin A1 Index Diameter D Solder ...