LP62S1024BX-55LLT AMIC Technology Corporation, LP62S1024BX-55LLT Datasheet
LP62S1024BX-55LLT
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LP62S1024BX-55LLT Summary of contents
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Document Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History 0.0 Initial issue 0.1 Add 32L Pb-Free TSSOP package type 1.0 Final version release 1.1 Change CCDR1 1.2 Add Pb-Free package type ...
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Features Power supply range: 2.7V to 3.6V Access times: 55/70 ns (max.) Current: Very low power version: Operating: 30mA(max.) Standby: 5uA (max.) Full static operation, no clock or refreshing required All inputs and outputs are directly TTL-compatible Common I/O using ...
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Pin Configurations SOP 1 VCC 32 NC A16 A15 31 2 A14 CE2 A12 A13 A11 A10 ...
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Pin Descriptions - SOP Pin No. Symbol 12, 23 A16 15, I GND 22 CE1 ...
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Recommended DC Operating Conditions = -25 ° +85 ° Symbol Parameter VCC Supply Voltage GND Ground V Input High Voltage IH V Input Low Voltage IL C Output Load L TTL Output Load Absolute Maximum ...
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Truth Table Mode CE1 H Standby X Output Disable L Read L Write L Note ° 1.0MHz) Capacitance (T A Symbol Parameter C * Input Capacitance Input/Output ...
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C to +85 ° C, VCC = 2.7V to 3.6V) AC Characteristics (T A Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t ACE1 Chip Enable Access Time t ACE2 t ...
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Timing Waveforms ( Read Cycle 1 Address D OUT ( Read Cycle 2 CE1 D OUT ( Read Cycle 3 CE2 D OUT (August, 2004, Version 1. ...
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Timing Waveforms (continued) (1) Read Cycle 4 Address OE CE1 CE2 D OUT Notes high for Read Cycle. 2. Device is continuously enabled CE1 = V 3. Address valid prior to or coincident with CE1 transition low. ...
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Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) Address CE1 CE2 OUT Notes measured from the address valid to the beginning of Write Write occurs during the overlap (t ...
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AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Including scope and jig. Figure 1. Output Load Data Retention Characteristics Symbol Parameter V DR1 VCC for Data ...
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Low VCC Data Retention Waveform (1) ( CE1 Controlled) VCC V CE1 IH Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC CE2 V IL (August, 2004, Version 1.2) DATA RETENTION MODE 3.0V t CDR ≥ CE1 ...
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... Ordering Information Part No. Access Time (ns) LP62S1024BM-55LLT LP62S1024BM-55LLTF LP62S1024BV-55LLT LP62S1024BV-55LLTF LP62S1024BX-55LLT LP62S1024BX-55LLTF LP62S1024BU-55LLT LP62S1024BU-55LLTF LP62S1024BM-70LLT LP62S1024BM-70LLTF LP62S1024BV-70LLT LP62S1024BV-70LLTF LP62S1024BX-70LLT LP62S1024BX-70LLTF LP62S1024BU-70LLT LP62S1024BU-70LLTF (August, 2004, Version 1.2) Operating Current Max. (mA LP62S1024B-T Series Standby Current Package Max. ( µ A) 32L SOP 32L Pb-Free SOP ...
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Package Information SOP (W.B.) 32L Outline Dimensions Seating Plane Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e 4. Dimension S includes ...
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Package Information TSOP 32L TYPE 20mm) Outline Dimensions y Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e 4. Dimension S includes end flash. ...
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Package Information TSSOP 32L TYPE 13.4mm) Outline Dimensions 0.10MM SEATING PLANE Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e 4. Dimension S includes ...
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Package Information 36LD CSP ( mm) Outline Dimensions Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). ...