A29040-70 AMIC Technology Corporation, A29040-70 Datasheet

A29040-70

Manufacturer Part Number

A29040-70

Description

Manufacturer

AMIC Technology Corporation

Datasheet

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Preliminary

Features

n 5.0V

n Access times:

n Current:

n Flexible sector architecture

n Embedded Erase Algorithms

General Description

PRELIMINARY

The A29040 is a 5.0 volt-only Flash memory organized as

524,288 bytes of 8 bits each. The 512 Kbytes of data are

further divided into eight sectors of 64 Kbytes each for

flexible sector erase capability. The 8 bits of data appear

on I/O

The A29040 is offered in 32-pin PLCC, TSOP, and PDIP

packages. This device is designed to be programmed in-

system with the standard system 5.0 volt VCC supply.

Additional 12.0 volt VPP is not required for in-system write

or erase operations. However, the A29040 can also be

programmed in standard EPROM programmers.

The A29040 has a second toggle bit, I/O

whether the addressed sector is being selected for erase,

and also offers the ability to program in the Erase Suspend

mode. The standard A29040 offers access times of 55, 70,

90, 120, and 150 ns, allowing high-speed microprocessors

to operate without wait states. To eliminate bus contention

the device has separate chip enable (

( WE ) and output enable (

The device requires only a single 5.0 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

- 8 uniform sectors of 64 Kbyte each

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

- 55/70/90/120/150 (max.)

- 20 mA typical active read current

- 30 mA typical program/erase current

- 1 A typical CMOS standby

- Embedded Erase algorithm will automatically erase

A hardware method of protecting sectors to prevent

any inadvertent program or erase operations within

that sector

the entire chip or any combination of designated

sectors and verify the erased sectors

- I/O

10% for read and write operations

while the addresses are input on A0 to A18.

(August, 2001, Version 0.5)

) controls.

), write enable

, to indicate

The A29040 is entirely software command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register contents

serve as input to an internal state-machine that controls

the erase and programming circuitry. Write cycles also

internally latch addresses and data needed for the

programming and erase operations. Reading data out of

the device is similar to reading from other Flash or EPROM

devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times

the program pulse widths and verifies proper program

margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm - an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper erase margin.

n Typical 100,000 program/erase cycles per sector

n 20-year data retention at 125 C

n Compatible with JEDEC-standards

n Erase Suspend/Erase Resume

n Package options

512K X 8 Bit CMOS 5.0 Volt-only,

- Embedded Program algorithm automatically writes

- Reliable operation for the life of the system

- Pinout and software compatible with single-power-

- Superior inadvertent write protection

- Provides a software method of detecting completion

- Suspends a sector erase operation to read data

- 32-pin P-DIP, PLCC, or TSOP(Forward type)

Data

and verifies bytes at specified addresses

supply Flash memory standard

of program or erase operations

from, or program data to, a non-erasing sector, then

resumes the erase operation

Uniform Sector Flash Memory

Polling and toggle bits

AMIC Technology, Inc.

A29040 Series

Related parts for A29040-70

A29040-70 Summary of contents

Page 1

... The A29040 has a second toggle bit, I/O whether the addressed sector is being selected for erase, and also offers the ability to program in the Erase Suspend mode. The standard A29040 offers access times of 55, 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention ...

Page 2

... The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29040 is fully erased when shipped from the factory. Pin Configurations DIP ...

Page 3

... Chip Enable Output Enable STB Timer Pin No. Description A0 - A18 Address Inputs - I/O Data Inputs/Outputs 0 7 Chip Enable CE Write Enable WE Output Enable OE VSS Ground VCC Power Supply 3 A29040 Series I Input/Output Buffers STB Data Latch Logic Y-Decoder Y-Gating X-decoder Cell Matrix AMIC Technology, Inc. ...

Page 4

... The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. A29040 Device Bus Operations ...

Page 5

... A29040 Series . Standard read cycle timings and I 0.5V. (Note that this is a more restricted CC .) The device enters the TTL standby IH is held The device requires the IH ) before it is ready to read data. CE input output from the device is ...

Page 6

... When using programming equipment, the autoselect mode requires V (11. address pinA9. Address ID pins A6, A1, and AO must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when Table 3. A29040 Autoselect Codes (High Voltage Method) Description A18 - A16 A15 - A10 Manufacturer ID: AMIC X Device ID: A29040 ...

Page 7

... Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" "1". 7 A29040 Series I/O . See "Write "1", or cause the 5 AMIC Technology, Inc ...

Page 8

... Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O Operation Status" for information on these status bits. 8 A29040 Series , I I/O . See Any ...

Page 9

... I/O and I command sequences. 2. See "I/O Status" for or I/O status bits, just A29040 Series START Write Erase Command Sequence Data Poll from System No Data = FFh ? Yes Erasure Completed : Sector Erase Timer" for more information. 3 Figure 2. Erase Operation AMIC Technology, Inc. ...

Page 10

... The Erase Resume command is valid only during the Erase Suspend mode. 11. The time between each command cycle has to be less than 50 s. PRELIMINARY (August, 2001, Version 0.5) Table 4. A29040 Command Definitions Bus Cycles (Notes First Second Addr Data Addr Data ...

Page 11

... Several bits, I/O , I/O , I/O , I/O , and I the A29040 to determine the status of a write operation. Table 5 and the following subsections describe the functions of these status bits. I method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. I/O ...

Page 12

... Under both these conditions, the system must issue the reset CE to control the read command to return the device to reading array data comparison A29040 Series and I Toggle Bit II" explains the algorithm. See 2 : Toggle Bit I" subsection. Refer to the Toggle ...

Page 13

... Version 0.5) switches from "0" the system can 3 ( Data Polling I/O is "1", the "0", the device 3 is high on the A29040 Series START Read I/O -I Read I/O -I (Note 1) Toggle Bit = Toggle ? Yes No I Yes Read I/O ...

Page 14

... See “I/O5: Exceeded Timing Limits” for more information. PRELIMINARY (August, 2001, Version 0.5) Table 5. Write Operation Status I/O I (Note 1) Toggle I Toggle 1 No toggle Data Data Toggle I A29040 Series I/O I/O I (Note 2) (Note 1) 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data Data 0 N/A N/A AMIC Technology, Inc ...

Page 15

... Maximum Negative Input Overshoot +0.8V -0.5V -2.0V Maximum Positive Input Overshoot VCC+2.0V VCC+0.5V 2.0V PRELIMINARY (August, 2001, Version 0.5) 20ns 20ns 20ns 20ns 20ns 20ns 15 A29040 Series AMIC Technology, Inc. ...

Page 16

... OUT = VCC 0.5 V VCC = 5. 12.0 mA, VCC = VCC Min -2.5 mA, VCC = VCC Min -100 A. VCC = VCC Min A29040 Series Min. Typ. Max. Unit 1.0 A 100 A 1 0.4 1.0 mA -0.5 V 0.8 2.0 VCC+0.5 V 10.5 V 12.5 0.45 V 2.4 V Min. ...

Page 17

... PRELIMINARY (August, 2001, Version 0.5) Description Test Setup Read Toggle and Data Polling t RC Addresses Stable t ACC OEH t CE High-Z 17 A29040 Series Speed -55 -70 -90 -120 Min 120 Max 120 IL IL Max 120 IL Max Min ...

Page 18

... WHWH2 WHWH2 (Note 2) VCC Set Up Time (Note 1) t VCS Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. PRELIMINARY (August, 2001, Version 0.5) Description WE low) 18 A29040 Series Speed -55 -90 -70 -120 Min 120 Min. 0 Min Min ...

Page 19

... Note : PA = program addrss program data, Dout is the true data at the program address. PRELIMINARY (August, 2001, Version 0. WPH A0h PD 19 A29040 Series Read Status Data (last two cycles WHWH1 Status D OUT AMIC Technology, Inc. ...

Page 20

... Note : SA = Sector Address Valid Address for reading status data. PRELIMINARY (August, 2001, Version 0. 555h for chip erase WPH 55h 30h 10h for chip erase 20 A29040 Series Read Status Data WHWH2 In Complete Progress AMIC Technology, Inc. ...

Page 21

... Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. PRELIMINARY (August, 2001, Version 0. Complement Complement Status Data Status Data 21 A29040 Series VA High-Z True Valid Data High-Z Valid Data True AMIC Technology, Inc. ...

Page 22

... PRELIMINARY (August, 2001, Version 0. Valid Status Valid Status (first read) (second read) . Illustration shows first two status cycle after command sequence, last status 6 22 A29040 Series VA VA Valid Status Valid Status (stop togging) AMIC Technology, Inc. ...

Page 23

... Program and I/O in the section "Write Operation Statue" for 6 2 Description -55 Min. 55 Min. Min. 40 Min. 25 Min. Min. Min. Min. Min. 30 Min. 20 Typ. Typ. 23 A29040 Series Erase Resume Erase Erase Read Complete Speed -70 -90 -120 -150 70 90 120 150 ...

Page 24

... DH PD for program 30 for sector erase 10 for chip erase Typ. (Note 1) Max. (Note 300 3.6 10.8 for further information A29040 Series Data Polling PA t WHWH1 or 2 I/O D OUT 7 = Complement of Data Input Array Data. 7 OUT Unit Comments sec Excludes 00h programming ...

Page 25

... Sampled, not 100% tested. 4. Test conditions 1.0MHz A Data Retention Parameter Minimum Pattern Data Retention Time PRELIMINARY (August, 2001, Version 0.5) Description Test Setup Test Setup Test Conditions 150 C 125 C 25 A29040 Series Min. -1.0V VCC+1.0V -100 mA +100 mA Typ. Max 7 8.5 ...

Page 26

... Input timing measurement reference levels Output timing measurement reference levels Device Under Test PRELIMINARY (August, 2001, Version 0.5) Table 6. Test Specifications - 0.0 - 3.0 1.5 1.5 5 Figure 7. Test Setup 26 A29040 Series All others Unit 1 TTL gate 100 0.45 - 2.4 V 0.8, 2.0 V 0.8, 2.0 V Diodes = IN3064 or Equivalent AMIC Technology, Inc. ...

Page 27

... Ordering Information Access Time Part No. (ns) A29040-55 A29040L-55 55 A29040V-55 A29040-70 A29040L-70 70 A29040V-70 A29040-90 A29040L-90 90 A29040V-90 A29040-120 A29040L-120 120 A29040V-120 A29040-150 A29040L-150 150 A29040V-150 PRELIMINARY (August, 2001, Version 0.5) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA A29040 Series ...

Page 28

... E 0.537 0.542 0.547 13.64 E 0.590 0.600 0.610 14.986 1 E 0.630 0.650 0.670 16.002 0.100 - L 0.120 0.130 0.140 3.048 - A29040 Series unit: inches/ Dimensions in mm Nom Max - - 5.334 - - 3.912 4.039 - 0.457 - - 1.270 - - 0.254 - 41.91 42.037 13.767 13.894 15.240 15.494 16 ...

Page 29

... D 0.390 0.410 0.430 9.91 E 0.585 0.590 0.595 14. 0.485 0.490 0.495 12. 0.075 0.090 0.095 1. 0.003 & G are for PC Board surface mount pad pitch A29040 Series unit: inches/ Dimensions in mm Nom Max - - 3. 2.80 2.93 0.71 0.81 0.46 0.54 0.254 0.35 13.97 14.05 11.43 11.51 1.27 1.42 12.95 13.46 10.41 10.92 14.99 15.11 12.45 12.57 2.29 2. 0.075 AMIC Technology, Inc ...

Page 30

... D 0.720 0.724 0.728 18. 0.315 0.319 e 0.020 BSC 0.779 0.787 0.795 19. 0.016 0.020 0.024 0. 0.032 - 0.020 0.003 - A29040 Series unit: inches/ Detail "A" Dimensions in mm Nom Max - - 1.20 - 0.15 1.00 1.05 0.22 0.27 - 0.20 18.40 18.50 - 8.00 8.10 0.50 BSC 20.00 20.20 0.50 0. AMIC Technology, Inc. ...

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