LP61L1024X-12 AMIC Technology Corporation, LP61L1024X-12 Datasheet

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LP61L1024X-12

Manufacturer Part Number
LP61L1024X-12
Description
Manufacturer
AMIC Technology Corporation
Datasheet
Document Title
Revision History
(August, 2004, Version 2.2)
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Rev. No.
2.0
2.1
2.2
History
Add product family and 32-pin TSSOP package
Add 36 ball BGA package type
Add Pb-Free package type
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
May 9, 2002
Issue Date
August 22, 2002
August 9, 2004
AMIC Technology, Corp.
LP61L1024
Remark
Final

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LP61L1024X-12 Summary of contents

Page 1

Document Title 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM Revision History Rev. No. History 2.0 Add product family and 32-pin TSSOP package 2.1 Add 36 ball BGA package type 2.2 Add Pb-Free package type (August, 2004, ...

Page 2

Features Single +3.3V power supply Access times: 12/15 ns (max.) Current: Operating: 170mA (max.) Standby: 10mA (max.) Full static operation, no clock or refreshing required All inputs and outputs are directly TTL compatible Common I/O using three-state output Output enable ...

Page 3

Pin Configurations SOJ 1 VCC NC 32 A16 A15 31 2 A14 CE2 3 30 A12 A13 A11 A10 ...

Page 4

Recommended DC Operating Conditions = 0 ° ° Symbol Parameter VCC Supply Voltage GND Ground V Input High Voltage IH V Input Low Voltage IL C Output Load L TTL Output Load Absolute ...

Page 5

Truth Table Mode CE1 H Standby X Output Disable L Read L Write L Note ° 1.0MHz) Capacitance (T A Symbol Parameter C * Input Capacitance Input/Output ...

Page 6

AC Characteristics (continued) Symbol Parameter Write Cycle t Write Cycle Time WC t Chip Enable to End of Write CW t Address Setup Time of Write AS t Address Valid to End of Write AW t Write Pulse Width WP ...

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Read Cycle 2 CE1 D OUT ( Read Cycle 3 CE2 t CLZ2 D OUT (1) Read Cycle 4 Address OE CE1 CE2 D OUT Notes high for Read Cycle. ...

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Timing Waveforms (continued) (6) Write Cycle 1 (Write Enable Controlled) Address CE1 CE2 OUT Write Cycle 2 (Chip Enable Controlled) Address CE1 CE2 OUT Notes measured from the address ...

Page 9

AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load +3.3V I/O * Including scope and jig. Figure 1. Output Load Data Retention Characteristics Symbol Parameter V DR1 VCC for Data ...

Page 10

... Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC 3.0V t CDR CE2 V IL Ordering Information Part No. Access Time (ns) LP61L1024S-12 LP61L1024S-12F LP61L1024V-12 LP61L1024V-12F 12 LP61L1024X-12 LP61L1024X-12F LP61L1024U-12 LP61L1024U-12F LP61L1024S-15 LP61L1024S-15F LP61L1024V-15 LP61L1024V-15F 15 LP61L1024X-15 LP61L1024X-15F LP61L1024U-15 LP61L1024U-15F (August, 2004, Version 2.2) DATA RETENTION MODE ≥ CE1 ≥ ...

Page 11

Package Information SOJ 32/32LD (300mil BODY) Outline Dimensions SEATING PLANE Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E doesn't include resin fins. 3. Dimension e reference only. 4. ...

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Package Information TSOP 32L TYPE 20mm) Outline Dimensions y Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e reference only. 4. Dimension S ...

Page 13

Package Information TSSOP 32L TYPE 13.4mm) Outline Dimensions 0.076MM SEATING PLANE Symbol Notes: 1. The maximum value of dimension D 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (August, 2004, Version ...

Page 14

Package Information 36LD CSP ( mm) Outline Dimensions Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). ...

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