LP621024DM-70LL AMIC Technology Corporation, LP621024DM-70LL Datasheet
LP621024DM-70LL
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LP621024DM-70LL Summary of contents
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Document Title 128K X 8 BIT CMOS SRAM Revision History Rev. No. History 1.1 Add Pb-Free package type (August, 2004, Version 1.1) LP621024D Series 128K X 8 BIT CMOS SRAM Issue Date Remark August 19, 2004 Final AMIC Technology, Corp. ...
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Features Single +5V power supply Access times: 55/70 ns (max.) Current: Very low power version: Operating: 70mA (max.) Standby: Full static operation, no clock or refreshing required All inputs and outputs are directly TTL-compatible General Description The LP621024D is a ...
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Block Diagram A0 A14 A15 A16 I/O 1 I/O 8 CE2 CE1 CONTROL CIRCUIT OE WE Pin Descriptions - DIP/SOP Pin No. Symbol Connection 2 - 12, 23 A16 Address Inputs 25 - 28, 31 ...
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Recommended DC Operating Conditions = 0 ° ° Symbol Parameter Supply Voltage GND Ground V Input High Voltage IH V Input Low Voltage IL C Output Load L TTL Output Load Absolute Maximum ...
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DC Electrical Characteristics (continued) Symbol Parameter Standby Power SB1 Supply Current I SB2 Output Low V OL Voltage Output High V OH Voltage Truth Table Mode CE1 H Standby X Output Disable L Read L Write L ...
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° C, VCC = 5V ± 10%) AC Characteristics (T A Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t ACE1 Chip Enable Access Time t ACE2 ...
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Timing Waveforms ( Read Cycle 1 Address D OUT ( Read Cycle 2 CE1 D OUT ( Read Cycle 3 CE2 CLZ2 OUT (August, 2004, Version 1. ...
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Timing Waveforms (continued) (1) Read Cycle 4 Address OE CE1 CE2 D OUT Notes high for Read Cycle. 2. Device is continuously enabled CE1 = V 3. Address valid prior to or coincident with CE1 transition low. ...
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Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) Address CE1 CE2 OUT Notes measured from the address valid to the beginning of Write Write occurs during the overlap (t ...
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AC Test Conditions Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load I/O * Including scope and jig. Figure 1. Output Load Data Retention Characteristics Symbol Parameter V DR1 V VCC for Data ...
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Low VCC Data Retention Waveform (1) ( CE1 Controlled) VCC 4.5V t CDR V CE1 IH Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC 4.5V t CDR CE2 V IL (August, 2004, Version 1.1) DATA RETENTION MODE ≥ 2V ...
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... Ordering Information Part No. Access Time (ns) LP621024D-55LL LP621024D-55LLF LP621024DM-55LL LP621024DM-55LLF LP621024DV-55LL LP621024DV-55LLF LP621024DX-55LL LP621024DX-55LLF LP621024D-70LL LP621024D-70LLF LP621024DM-70LL LP621024DM-70LLF LP621024DV-70LL LP621024DV-70LLF LP621024DX-70LL LP621024DX-70LLF (August, 2004, Version 1.1) Operating Current Max. (mA LP621024D Series Standby Current Package Max. ( µ ...
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Package Information P-DIP 32L Outline Dimensions Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E 3. Dimension S includes end flash. (August, 2004, Version 1. Base Plane Seating ...
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Package Information SOP (W.B.) 32L Outline Dimensions Seating Plane Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e reference only. 4. Dimension S ...
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Package Information TSOP 32L TYPE 20mm) Outline Dimensions y Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e reference only. 4. Dimension S ...
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Package Information TSSOP 32L TYPE 13.4mm) Outline Dimensions 0.10MM SEATING PLANE Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e reference only. 4. ...