ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 167
ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
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- ATTINY25_AUTOMOTIVE PDF datasheet #3
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21.6
7701E–AVR–02/11
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus
while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and
MISO (output). After RESET is set low, the Programming Enable instruction needs to be exe-
cuted first before program/erase operations can be executed. NOTE, in
167, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated
for the internal SPI interface.
Figure 21-1. Serial Programming and Verify
Note:
Table 21-9.
When programming the EEPROM, an auto-erase cycle is built into the self-timed program-
ming operation (in serial mode only), and there is no need to first execute the chip erase
instruction. The chip erase operation turns the content of every memory location in both the
program and EEPROM arrays into 0xFF.
Depending on the CKSEL fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
1. If the device is clocked by the internal oscillator, it is not needed to connect a clock source to
Symbol
MOSI
MISO
SCK
the CLKI pin.
Pin Mapping Serial Programming
Atmel ATtiny24/44/84 [Preliminary]
MOSI
MISO
SCK
ck
ck
Pins
PA6
PA5
PA4
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
RESET
GND
(1)
VCC
I/O
O
I
I
+1.8 - 5.5V
ck
ck
>= 12MHz
>= 12MHz
Description
Serial Data in
Serial Data out
Serial Clock
Table 21-9 on page
167
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