ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet - Page 92
ATtiny25 Automotive
Manufacturer Part Number
ATtiny25 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY25_AUTOMOTIVE.pdf
(7 pages)
3.ATTINY25_AUTOMOTIVE.pdf
(196 pages)
Specifications of ATtiny25 Automotive
Flash (kbytes)
2 Kbytes
Pin Count
8
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY25_AUTOMOTIVE PDF datasheet #2
- ATTINY25_AUTOMOTIVE PDF datasheet #3
- Current page: 92 of 225
- Download datasheet (4Mb)
14.2.1
92
Atmel ATtiny24/44/84 [Preliminary]
Registers
Figure 14-1. 16-bit Timer/Counter Block Diagram
Note:
The timer/counter (TCNT1), output compare registers (OCR1A/B), and input capture register
(ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit
registers. These procedures are described in the section
94. The timer/counter control registers (TCCR1A/B) are 8-bit registers, and have no CPU
access restrictions. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visi-
ble in the timer interrupt flag register (TIFR). All interrupts are individually masked with the
timer interrupt mask register (TIMSK). TIFR and TIMSK are not shown in the figure.
The timer/counter can be clocked internally, via the prescaler, or by an external clock source
on the T1 pin. The clock select logic block controls which clock source and edge the
timer/counter uses to increment (or decrement) its value. The timer/counter is inactive when
no clock source is selected. The output from the clock select logic is referred to as the timer
clock (clk
1. See
T
1
).
Figure 1-1 on page 2
Timer/Counter
TCCRnA
OCRnA
OCRnB
TCNTn
ICRn
=
=
Direction
Count
Clear
for Timer/Counter1 pin placement and description.
Control Logic
TOP
=
TCCRnB
Values
BOTTOM
Fixed
TOP
ICFn (Int.Req.)
(1)
clk
Detector
Edge
=
Tn
0
“Accessing 16-bit Registers” on page
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
Generation
Generation
( From Prescaler )
Waveform
Waveform
Canceler
Detector
Noise
Edge
Comparator Ouput )
( From Analog
7701E–AVR–02/11
OCnA
OCnB
ICPn
Tn
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