ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 189

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.3
16.3.1
16.4
8077H–AVR–12/09
Address
+0x00
Register Description
Register Summary
CTRLA - Hi-Res Control Register A
Name
CTRLA
• Bit 7:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1:0 - HREN[1:0]: Hi-Resolution Enable
Enables Hi-Resolution mode for a Timer/Counter according to
Setting one or both HREN bits will enable Hi-Resolution waveform generation output for the
entire general purpose I/O port. This means that both Timer/Counters connected to the same
port must enable Hi-Res if both are used for generating PWM or FRQ output on pins.
Table 16-1.
Bit
+0x00
Read/Write
Initial Value
Bit 7
HREN[1:0]
Hi-Resolution Enable
00
01
10
11
Bit 6
R
7
–
0
R
6
–
0
Bit 5
Hi-Resolution Enabled
None
Timer/Counter 0
Timer/Counter 1
Both Timer/Counters
5
–
R
0
Bit 4
R
4
–
0
Bit 3
R
3
–
0
Bit 2
Table
R
2
–
0
16-1.
Bit 1
R/W
1
0
HREN[1:0]
HREN[1:0]
XMEGA A
R/W
Bit 0
0
0
CTRLA
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