ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 30

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.16
4.16.1
4.16.2
4.16.3
8077H–AVR–12/09
Register Description – Fuses and Lockbits
FUSEBYTE0 - Non-Volatile Memory Fuse Byte 0 - JTAG User ID
FUSEBYTE1 - Non-Volatile Memory Fuse Byte1 - Watchdog Configuration
FUSEBYTE2 - Non-Volatile Memory Fuse Byte2 - Reset Configuration
• Bit 7 - JTAGUID[7:0]: JTAG USER ID
These fuses can be used to set the default JTAG USER ID for the device. During reset, the
JTAGUID fuse bits will be loaded into the MCU JTAG User ID Register.
• Bit 7:4 - WDWPER[3:0]: Watchdog Window Timeout Period
The WDWPER fuse bits are used to set initial value of the closed window for the Watchdog
Timer in Window Mode. During reset these fuse bits are automatically written to the WPER bits
Watchdog Window Mode Control Register, refer to
Control Register” on page 120
• BIT 3:0 - WDPER[3:0]: Watchdog Timeout Period
The WDPER fuse bits are used to set initial value of the Watchdog Timeout Period. During reset
these fuse bits are automatically written to the PER bits in the Watchdog Control Register, refer
to
• Bit 7 - Reserved
This fuse bit is reserved. For compatibility with future devices, always write this bit to one when
this register is written.
Bit
+0x02
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
Section 11.7.1 ”CTRL – Watchdog Timer Control Register” on page 119
R/W
R/W
7
0
7
0
R/W
7
–
1
R/W
R/W
WDWPER[3:0]
6
0
6
0
BOOTRST
R/W
6
1
for details.
R/W
R/W
5
0
5
0
R/W
5
–
1
R/W
R/W
4
0
4
0
JTAGUID[7:0]
R/W
4
–
1
R/W
R/W
3
0
3
0
Section 11.7.2 ”WINCTRL – Window Mode
R/W
3
–
1
R/W
R/W
2
0
2
0
WDPER[3:0]
R/W
2
–
1
R/W
R/W
1
0
1
0
R/W
1
1
BODPD[1:0]
R/W
R/W
for details.
0
0
0
0
XMEGA A
R/W
0
1
FUSEBYTE0
FUSEBYTE1
FUSEBYTE2
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