ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 348

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.3.5
29.3.5.1
8077H–AVR–12/09
Serial Transmission
Drive contention and collision detection
When a data transmission is initiated (by the PDI Controller), the transmitter simply shifts the
start bit, data bits, the parity bit, and the two stop bits out on the PDI_DATA line. The transmis-
sion speed is dictated by the PDI_CLK signal. While in transmission mode, IDLE bits (high bits)
are automatically transmitted to fill possible gaps between successive DATA characters. If a col-
lision is detected during transmission, the output driver is disabled and the interface is put into a
RX mode waiting for a BREAK character.
In order to reduce the effect of a drive contention (the PDI and the programmer drives the
PDI_DATA line at the same time), a mechanism for collision detection is supported. The mecha-
nism is based on the way the PDI drives data out on the PDI_DATA line. As shown in Figure 7,
the output pin driver is only active when the output value changes (from 0-1 or 1-0). Hence, if
two or more successive bit values are the same, the value is only actively driven the first clock
cycle. After this point the output driver is automatically tri-stated, and the PDI_DATA pin has a
bus-keeper responsible for keeping the pin-value unchanged until the output driver is re-enabled
due to a bit value change.
Figure 29-7. Driving data out on the PDI_DATA using bus-keeper
If the programmer and the PDI both drives the PDI_DATA line at the same time, the situation of
drive contention will occur as illustrated in
kept for two or more clock cycles, the PDI is able to verify that the correct bit value is driven on
the PDI_DATA line. If the programmer is driving the PDI_DATA line to the opposite bit value
than what the PDI expects, a collision is detected.
Output enable
Driven output
PDI_CLK
PDI_DATA
1
0
Figure 29-8 on page
1
1
0
349. Every time a bit value is
0
XMEGA A
1
348